Other Parts Discussed in Thread: TCI6638K2K
e have designed a TCI6638K2K custom board, based on EVM6638 rev 2.0 We have replaced the microcontroller with a CPLD for power sequencing. The power rails seem fine using/monitoring with the fusion GUI. We have replace the DDR3A and DDR3B with micron MT41J256M16HA-125-E Layout rules were followed as in the hardware design guide I am using the Gel file for EVM modified for new memeory parts I am using the EVM gel file with the changes I have made for DDR3B I am not testing the DDR3A at the moment.
I used DDR3 Reg Calc v4.xls which seems to show different register feilds in Keystone II DDR3 Memory Controller SPRUHN7A. ( Here are some settings I am using:
DDR3A_REMAP_EN=0 (DEVSTAT = 0x00000001)(bootmode = 0x00000000)
DDR3B_DTPR0 = 0x9D5CBB66;
DDR3B_DTPR1 = 0x228503D0;
DDR3B_DTPR2 = 0x100198AA;
DDR3B_ZQ0CR1 = 0x0000005D;
DDR3B_ZQ1CR1 = 0x0000005B;
DDR3B_ZQ2CR1 = 0x0000005B;
DDR3B_SDCFG = 0x6480CE62; //bit 24 is marked Reserved in manual!! =0)
//DDR3B_SDCFG = 0x6580CE62; //bit 24 marked above as DDQS=1)
DDR3B_SDTIM1 = 0x166C5855; DDR3B_SDTIM2 = 0x0000154A; DDR3B_SDTIM3 = 0x421DFF53; DDR3B_SDTIM4 = 0x543F07FF;
The clocks and PLLs seem OK and I can connect to C66x cores and examine their memory. I connect via JTAG to C66x-0,
-I see that during initialization of DDR3
DDR3B_PGSR0=0x8010000F (ZCERR=1) and later
DDR3B_PGSR0=0x81F001FF. (WLERR=1, QSGERR=1, WLAERR, RDERR=1, WDERR=0, REERR=0, WEERR=0)
-When I access DDR3 memory using Memory Browser, I have a crash:
Trouble Reading Memory Block at 0x60000000 on Page 0 of Length 0x9b0: (Error -1202 @ 0x60000000) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 5.1.73.0)
other Observations:
The section of the Gel that turns on all modules(Set_Psc_All_On(); reports many timeout errors:
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=25!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=26!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=18, md=27!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=28!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=29!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=30!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=31!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=32!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=33!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=21, md=34!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=35!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=36!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=37!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=38!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=39!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=40!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=41!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=42!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=43!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=44!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=45!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=46!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=26, md=47!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=27, md=48!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=29, md=50!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
Thanks
