Hi community,
I have done Manhattan length calculations of a configuration with two DDR2 memories conected to AM3517.
The AM3517 is placed at X,Y = 0,0 mm and the two DDR2 memories are placed at X,Yoffset = -44,+/-16 mm, which is the maximum allowable distance from AM3517 according to table 6-17 in the AM3517 datasheet.
DDR2 CLK and ADDR_CTRL Routing (table 6.23):
CACLM is the longest Manhattan distance of the CLK and ADDR_CTRL net classes. (3 points in nets)
CACLM (SDRC_NCAS) = 86,95mm
DQS and Dx Routing Specification (table 6-24):
DQLM is the longest Manhattan distance of each of the DQS and Dx net classes (2 points in nets):
Signal net class DQ0 (SDRC_D[7:0] / SDRC_DM0 / SDRC_DQS0p / SDRC_DQS0n)
DQLM0 (SDRC_D4) = 54,10 mm
Signal net class DQ1 (SDRC_D[15:8] / SDRC_DM1 / SDRC_DQS1p / SDRC_DQS1n)
DQLM1 (SDRC_D12) = 51,55 mm
Signal net class DQ2 (SDRC_D[23:16] / SDRC_DM2 / SDRC_DQS2p / SDRC_DQS2n)
DQLM2 (SDRC_D21) = 52,80 mm
Signal net class DQ3 (SDRC_D[31:24] / SDRC_DM3 / SDRC_DQS3p / SDRC_DQS3n)
DQLM3 (SDRC_D29) = 47,00 mm
If the memories are placed closer to the AM3517, is it then allowed to increase the lengths of the different signal net classes to be longer than the corresponding CACLM and DQLMx lengths at the actual placement (while being shorter than the CACLM and DQLMx lengths at the the maximum allowable distance from AM3517) ?
Regards,
Michael Iversen
