query regarding the 1GB memory configuration file: \vision_sdk\build\tda2xx\mem_segment_definition_1024mb.xs
As per the reference content below, DDR3_BASE_SIZE_0 - 512 MB is only split amongst the various processor cores for code/data sections. We are in need of changing the memory configuration to accommodate more dynamic memory allocation.
We were successful in changing the memory configuration with in the “First 512 MB - cached” section but once we try to pull in some memory from the “Second 512 MB - non-cached” section, we are unable to see the boot up UART messages and we guess, the application execution might have stopped.
In this regard, please share your inputs on the following :
- Is the “First 512 MB - cached” configuration fixed or can we increase the size allocated for the various processor cores?
- If yes, how much can be pulled from the “Second 512 MB - non-cached” and what is the impact of the same on the system memory configuration at large?
Reference content from the memory configuration file:
DDR3_ADDR = 0x80000000;
DDR3_SIZE = 1024*MB;
DDR3_BASE_ADDR_0 = 0x80000000;
DDR3_BASE_SIZE_0 = 512*MB;
DDR3_BASE_ADDR_1 = 0xA0000000;
DDR3_BASE_SIZE_1 = 512*MB;
Regards,
Mahesh