SRIO Messages Dropped

Nick Borton

Hello,

I am attempting to debug an issue where my 6472 appears to be dropping SRIO messages sent to it by an FPGA. The ERR_DET register indicates and RX CPPI Security issue. From the ID_CAPT register is appears that the destination and source IDs are as expected.

The following code is configuring the map registers:

SrioBase_regs->MAP[index].RXU_MAP_L = CSL_FMK(SRIO_RXU_MAP_L_LETTER_MASK, 0) |
                                         CSL_FMK(SRIO_RXU_MAP_L_MAILBOX_MASK, 0) |
                                         CSL_FMK(SRIO_RXU_MAP_L_LETTER, 0) |
                                         CSL_FMK(SRIO_RXU_MAP_L_MAILBOX, 0) |
                                         CSL_FMK(SRIO_RXU_MAP_L_SOURCEID, 0xBEEF);
SrioBase_regs->MAP[index].RXU_MAP_H = CSL_FMK(SRIO_RXU_MAP_H_TT, 1) |
                                         CSL_FMK(SRIO_RXU_MAP_H_QUEUE_ID, index) |
                                         CSL_FMK(SRIO_RXU_MAP_H_PROMISCUOUS, 1) |
                                         CSL_FMK(SRIO_RXU_MAP_H_SEGMENT_MAPPING, 1);

I think I have the map registers configured to accept all messages.

The head pointers for the associated queues have been configured.

I'm at a loss as to where to look as to why the message may be throwing that error. Are there any issues with the FPGA sending a "multi segment" packet with only one segment?

Thanks!

over 11 years ago

0 Clinton Rodgers over 11 years ago

TI__Genius 13235 points

Hi norton256,

Thanks for posting. Could you give us some more insight into your setup?

Is the C6472 device on a TI evaluation modole or a custom board?
Are you use 1 or 2 of the 1x ports?
Are you using Direct IO operation or message passing?
1. If message passing, what types of messages are you using?

Can you also provide the ERR_DET register dump, as well as the SPn_ERR_STAT and SPn_ERR_DET registers?

Can you try disabling the RX_CPPI_SECURITY_ENABLE bit in the ERR_EN register and see if the behavior changes?

Thanks,

Clinton

0 Nick Borton over 11 years ago in reply to Clinton Rodgers

Genius 3595 points

Hi Clinton,

We are running on a custom board, with the FPGA and DSP on the same PCB. We are currently only using one of the 1x ports.

We are using message passing, and the problem seemed to be that the FPGA was using 8 bit IDs. Once the FPGA switched to 16 bit, the message made its way through.

Is there a global setting some where which puts the DSP into 8 bit vs 16 bit ID mode? it seems to support them simultaneously.

Thanks!

0 Clinton Rodgers over 11 years ago in reply to Nick Borton

TI__Genius 13235 points

norton256,

Glad you were able to track down your issue. The "TT" field sets whether 8 or 16 bit device IDs are used. You can take a look at the MCSDK SRIO loopback example for C6472 for more setup information.

http://www.ti.com/tool/bioslinuxmcsdk

Thanks,

Clinton

0 Nick Borton over 11 years ago in reply to Clinton Rodgers

Genius 3595 points

So just to make sure I have this right. If the RX Map Register is in promiscuous mode, it still checks the TT field for device ID size?

Thanks

0 Clinton Rodgers over 11 years ago in reply to Nick Borton

TI__Genius 13235 points

I'll have to do some more research. Are you using type 11 messages? There may be an issue with the return messages for type 11 and other transactions that require a response, if the communicating devices are not using the same size IDs.

Thanks,

Clinton

0 Nick Borton over 11 years ago in reply to Clinton Rodgers

Genius 3595 points

Yes, we are using Type 11 messages

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SRIO Messages Dropped