McBSP setting on OMAP-L138

Kanae

Our customer's program for OMAP-L138 EVM has problem to McBSP setting.
When the program is running on OMAP-L138EVM connected FPGA EVM,
the register setting are following values.

Problem 1: DX has 2-bit delay when EVM transmits data setting 0-bit delay.
                  Please refer to the connection diagram and waveform in the attached file.

4370.E2E_OMAP-L138_McBSP.pdf

Problem 2: It is always reading back 0 from DRR when EVM receives data.
                   At the time, the waveforms of FSR, CLKR and DR are correct.

How can I set to solve these problems? Does it have any fixed sequence?


Register value at Transmitting data:
DXR= 55FF55FF
SPRC= 02030000
RCR= 00400040
XCR= 00410040
SRGR= B0110001
MCR= 00000000
PCR= 00000080

Register value at receiving data:
DRR= 00000000
DXR= 55F055F0
SPCR= 02030001
RCR= 00400040
XCR= 00400040
SRGR= B0110001
MCR= 00000000
PCR= 00000080

Kawakami

over 15 years ago

0 tlee over 15 years ago

TI__Guru 62975 points

Kawakami,

Here's what I see:

SPCR = 0x02030000 = No EMU Halt, TX Ready
XCR = 0x00410040 = Single-phase frames, 1 word/frame, 16-bits/word, 1-bit delay (I assume the delay was leftover from the 1-bit delay example)
RCR = 0x00400040 = Single-phase frames, 1 word/frame, 16-bits/word
SRGR = 0xB0110001 = Resync CLKG on every FSR, Generate CLKG from CLKX, (Bit 28 FSGM ignored), Frame period = 18 CLKG periods, CLKG = CLKX/2
MCR = 0x00000000 = No multichannel
PCR = 0x00000080 = Frame Sync & Clock pins are input, No Frame Sync or Clock Inversion, CLKG is derived from CLKX, do not use CLKG

Since PCR does not enable CLKG, I'm going to ignore the CLKG settings. The thing that stands out to me then is that the Frame Period is set to 18 when the data size is 16. This might explain why the transmit is delayed and the receive data is dropped.

-Tommy

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McBSP setting on OMAP-L138