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VAYU board pixel clock

Kumar Kumar
Prodigy 180 points

Hi,

I am trying to understand how to change the pixel clock(vout1_pclk) in the VAYU board. From the device tree, "tfc_s9700" panel is used in VAYU board. If I change the pixel clock in the "panel-tfcs9700.c" driver, then "vout1_pclk" will also be changed or Display subsystem source need to update to change "vout1_pclk".

  • 0
    TI__Guru**** 161600 points

    Hi Kumar,

    Yes, the video timings structure defined in panel-tfcs9700.c assigns the value of the pixel clock that the tfcs9700 panel uses.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 180 points

    Hi Yordan,

    Thanks for the reply.

    My doubht here is, under section 11.2.4.1 of DRA75X/74X TRM it was explained that how to set the pixel clock values. If we set the pixel clock in video timings structure of the panel driver then display subsystem source will internally taken care for setting the values explained under section 11.2.4.1 of DRA75X/74X.

  • 0 in reply to Kumar Kumar
    TI__Guru**** 161600 points

    Hi,

    If you're using the tfcs9700 panel, then yes only changing the .pixel_clock value is needed in order to change pixel clock.

    You can check the board-support/linux/drivers/video/omap2/dss/dispc.c driver to verify that display controller driver uses these values to configure its registers, see the relevant code fragment:

    void dispc_mgr_set_timings(enum omap_channel channel,
            const struct omap_video_timings *timings)
    {
        unsigned xtot, ytot;
        unsigned long ht, vt;
        struct omap_video_timings t = *timings;

        DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);

        if (!dispc_mgr_timings_ok(channel, &t)) {
            BUG();
            return;
        }

        if (dss_mgr_is_lcd(channel)) {
            _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
                    t.vfp, t.vbp, t.vsync_level, t.hsync_level,
                    t.data_pclk_edge, t.de_level, t.sync_pclk_edge);

            xtot = t.x_res + t.hfp + t.hsw + t.hbp;
            ytot = t.y_res + t.vfp + t.vsw + t.vbp;

            ht = (timings->pixel_clock * 1000) / xtot;
            vt = (timings->pixel_clock * 1000) / xtot / ytot;

            DSSDBG("pck %u\n", timings->pixel_clock);
            DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
                t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
            DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
                t.vsync_level, t.hsync_level, t.data_pclk_edge,
                t.de_level, t.sync_pclk_edge);

            DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
        } else {
            if (t.interlace == true)
                t.y_res /= 2;
        }

        dispc_mgr_set_size(channel, t.x_res, t.y_res);
    }
    EXPORT_SYMBOL(dispc_mgr_set_timings);

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 180 points

    Thanks Yordan.

    I have understood now.