Questions about SRIO device init

Clement FR

Genius 4750 points

Hello all,

I'm using the C6678 SRIO peripheral.

I have some questions about the device init as found in the SRIOLoopbackDioIsr SRIO LLD example.

The final system will have one board with several C6678 and a SRIO switch.

Basically the DSP will only use DirectIO writes, reads and doorbells. No message passing, nothing else.

My questions :

a) in the Processing Element Features CAR

what does Extended Features "PE has extended features list; the extended features pointer is valid" mean ?
what are these features ?

b) for the source/destination operations CAR : OK

Let's say I disable "atomic clear" in the SOURCE op car and enable it in the DESTINATION op car.

It means the DSP won't be able to SEND SRIO atomic clear packets right ?
and that I'll still be able to receive them right ?

OK it's right.

c) about Base Device ID CSR : OK

My Processing Element is a Processor (not an endpoint)
So is it really useful for my use case to call CSL_SRIO_SetDeviceIDCSR ? YES

In the documentation it says
"This is the base ID of the device in small common transport system (endpoints only)."

here endpoint can refer to a processor too.

d) about DEV_ID CSR : Partially OK

In the documentation it says "DeviceIdentity field value should be programmed to be 0x009D"
and "Identifies the type of device. Vendor specific"

but in the device_init code we have
CSL_SRIO_SetDeviceInfo (hSrio, DEVICE_ID1_16BIT, DEVICE_VENDOR_ID, DEVICE_REVISION);

with DEVICE_ID1_16BIT = 0xBEEF

to me it's not the right value... and why do we even set it if it's hard wired ?

e) about HOST_BASE_ID_LOCK : OK

The call :

CSL_SRIO_SetHostDeviceID (hSrio, DEVICE_ID1_16BIT);

in the documentation it says "This is the base ID for the Host PE that is initializing this PE."

Host Device ID = Base device id because here our DSP (processing element) is initializating (no discovery) itself right ?

yes it would matter in a system with discovery

f) The port link time-out control CSR (SP_LT_CTL) : OK

In the init example this timeout is set to 0xFFF (4095)

Why this choice ? How do I know the optimum setting for my system ?

see ClintonRodgers reply

I'll add other questions later.

Thank you

Clement

over 11 years ago

0 Brandy Jabkiewicz over 11 years ago

Mastermind 6325 points

Hello Clement,

I think I can help you clear up your questions about IDs.

First there are two IDs. One is fixed. It is called the DEV_ID and it is vendor specific. According to sprugw1a.pdf, it is read-only so this should not be a worry for you. It will have nothing to do with how you address each DSP. You can read the DEV_ID with this CSL function call.

CSL_SRIO_GetDeviceInfo

The other DeviceID that you reference you will use to send messages to each DSP, it should be unique for each DSP. For instance, in my code, each DSP is 0xD1, 0xD2.... etc. This is how you set those IDs. Then when you want to send a DIO message, you will use these values to address the desired DSP.

    /* Set the 16 bit and 8 bit identifier for the SRIO Device. */
    CSL_SRIO_SetDeviceIDCSR (hSrio, deviceID_8bit, deviceID_8bit | (deviceID_8bit << 8) );

    Uint8 myDeviceId8 = 0x00;
    Uint16 myDeviceId16 = 0x0000;
    CSL_SRIO_GetDeviceIDCSR(hSrio, &myDeviceId8, &myDeviceId16);
    LOG_DEBUG("Device ID8: 0x%x Device ID16 0x%x", myDeviceId8, myDeviceId16);

The Host Lock register is for when you want to do system enumeration dynamically instead of statically. There are few good articles about it. Here is one that I liked: http://www.edn.com/design/systems-design/4324420/Software-considerations-around-RapidIO-designs

While the CSL exists to write your own host Lock register, chances are you will be using maintenance packets to read/write another DSP's host lock register. In this manner, you can make sure there are no collisions when trying to initialize the system.

I have another post with a lot of good information, sounds like you are just starting out. My system was very similar, one board with 4DSPs and a switch. Perhaps this will help you get started.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/170264.aspx?pi303753=1

Brandy

0 Brandy Jabkiewicz over 11 years ago in reply to Brandy Jabkiewicz

Mastermind 6325 points

Also, TI experts, for the record, I just noticed that while the sprugw1a (sec 3.12.1) says the vendor ID is read only, there is code in your sample project and the CSL library that tries to set the vendor ID. Can you comment please?

    /* Set the Device Information */
    CSL_SRIO_SetDeviceInfo (hSrio, deviceID_8bit, DEVICE_VENDOR_ID, DEVICE_REVISION);

    /* Set the Assembly Information */
    CSL_SRIO_SetAssemblyInfo(hSrio, DEVICE_ASSEMBLY_ID, DEVICE_ASSEMBLY_VENDOR_ID, 
                             DEVICE_ASSEMBLY_REVISION, DEVICE_ASSEMBLY_INFO);

0 Clement FR over 11 years ago in reply to Brandy Jabkiewicz

Genius 4750 points

Hello Brandy,

Thank you for your reply.

Yes I'm just getting started on SRIO. I've already seen some of your posts, it's helpful.

Just two notes :
- in our team I'm not in charge of the switch configuration and routing tables. I'm in charge of the applicative DSPs communication through SRIO.
Basically we have 4 applicative DSP, 1 Host DSP and 1 switch. The Host DSP is responsible for the system init (including the SRIO switch).
- we don't use the socket-based SRIO LLD (for various reasons) : only the CSL is used.

About Device and Assembly information, yes it is confusing that it is set in software instead of hard coded values.
I think I read somewhere on the support forums that they were settable before the boot complete was set.

Thank you for the good article link and the info on the Host lock register.

I'm clear on c) and mostly d) and e).

a), b) and f) remains.

Clement

0 Clement FR over 11 years ago in reply to Clement FR

Genius 4750 points

g) SERDES config

For now I want to configure on the EVM C6678 :

link rate 5 Gp/s, ref clock 312.5MHz and LOOPBACK mode on (CSL_SRIO_SetLoopbackMode)

My PLL setting CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

what should I use for SERDESRxConfig and SERDESTxConfig ?

I only have the default values 0x00440495 and 0x00180795

Thanks

Clement

0 Ganapathi Dhandapani95 over 11 years ago in reply to Clement FR

TI__Mastermind 28085 points

Hi Clement,

Q: said:
b) for the source/destination operations CAR
Let's say I disable "atomic clear" in the SOURCE op car and enable it in the DESTINATION op car.

It means the DSP won't be able to SEND SRIO atomic clear packets right ?
and that I'll still be able to receive them right ?

Yes your understanding is correct. I will check with my team and try to answer remaining question.

Thanks,

0 Clement FR over 11 years ago in reply to Ganapathi Dhandapani95

Genius 4750 points

Hi,

Thank you for your answer.

Clement

0 Ganapathi Dhandapani95 over 11 years ago in reply to Clement FR

TI__Mastermind 28085 points

Hi Clement,

Ans:G

Your PLL setting value(0x241) is correct for Link Rate 5 Gp/s, Ref clock 312.5MHz and LOOPBACK mode on (CSL_SRIO_SetLoopbackMode)

CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

5 Gbps SERDESRxConfig (rxConfig = 0x00440495;) and SERDESTxConfig (txConfig = 0x00180795;)

Please take a look at section 2.3.1.4 SerDes Configuration Example on SRIO user guide(SPRUGW1B).

Thanks,

0 Clement FR over 11 years ago in reply to Ganapathi Dhandapani95

Genius 4750 points

Hi Ganapathi,

Thank you for the confirmation.

Clement

0 Clinton Rodgers over 11 years ago

TI__Genius 13235 points

Hi Clement,

For (f), take a look at the following threads. There will be some clarification added to the next revision of the SRIO user guide based on this information.

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/309418/1081657.aspx#1081657

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/294447/1044428.aspx#1044428

I believe that leaves (a) as your last open question on this thread. I'll take a look and provide some feedback.

Thanks,

Clinton

0 Clement FR over 11 years ago in reply to Clinton Rodgers

Genius 4750 points

Hi Clinton,

Thank you for your reply and the links. It is helpful.

When can I expect the next revision of the SRIO user guide ? What is the approximate timeframe : less than a month, several months ?

There is still (d) also. BrandyJ brought some replies but not to everything. Especially, these remains :

"why do we even set it if it's hard wired ?" "why in the UG it is written 'program it to 0x009D' "

Regards,

Clement

0 Clinton Rodgers over 11 years ago in reply to Clement FR

TI__Genius 13235 points

Hi Clement,

I'll take a look into (d) as well.

I would expect it published to the web within the next couple months, if not sooner. We're still working through the changes. Most of the changes originate from threads in these forums, so you should be able to search here in the meantime. If you can't find your answer in the documentation or searching the forums, feel free to create a new post.

Thanks,

Clinton

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