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K2HK: EMAC Digital loopback

Expert 1800 points

Other Parts Discussed in Thread: 66AK2H12

Hi,

I am debugging EMAC interface with SGMII_LINK_MAC_MAC_FORCED configuration on my custom board  based on 66AK2H12.   The link speed is 1Gig.  The SGMII port 0 and 1 are interfaced with the FPGA.   

 I would like to do loopback tests on K2H EVM with SGMII_LINK_MAC_MAC_FORCED configuration.  We have only a PHY loopback in K2H U-boot POST.

 I tried SGMII internal loopback by modifying the U-boot POST EMAC test on the K2H EVM.  I could not succeed.  

I wanted to verify EMAC interface on our custom hardware.  Therefore, it will be very useful if I can perform MAC, SGMII and SERDES loopback on the EVM so that I can do the similar tests on the custom hardware.

Thanks

Rams

  • Hi,

    I am now using the EVM to do Digital loopback.  

    EVMs Ports 2 and 3 are setup as SGMII_LINK_MAC_MAC_FORCED.  The U-boot POST does PHY loopback for ports 0 and 1.

    I have modified u-boot POST and added functions for setting up Digital loopback for ports 2 and 3.

    The steps for Digital Loopback as described in sprugv9d page 72 are follows

    1 Clear to 0 the MR_AN_ENABLE bit in the SGMII_CONTROL Register
    2 Write to 1 the RT_SOFT_RESET bit in the SOFT_RESET Register
    3 Write to 1 the LOOPBACK bit in the SGMII_CONTROL Register
    4 Write to zero the RT_SOFT_RESET bit in the SOFT_RESET Register

    I followed the above steps, but I could not get it working.  After the above configuration, I could not receive the packet back.  Are there any additional steps required?

    Please clarify

    Thanks

    Rams

  • Rams,

    Please find an EMAC test code at: pdk_keystoneX_X_X_X_X\packages\ti\drv\pa\example\emacExample
    To get the latest release, please go to the MCSDK product folder at MCSDK Product Page.
    The emacExample project is designed to run in loopback modes. This test code will support the following two loopback modes, as per below Macros.
    CPSW_LOOPBACK_INTERNAL(default): The transmitted packet is loopbacked at the SGMII through SGMII internal loopback
    CPSW_LOOPBACK_EXTERNAL: The transmitted packet should bo loopbacked by application outsite the SoC
    This wiki will help you, how to test on the board using CCS.
    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Developing_PDK

  • Hi,

    Thanks for the response. I have already referred the code in PDK.  We are currently debugging our custom hardware and we want to run the test both on EVM and custom hardware to compare and debug the issue on our hardware. The example code what you refer could be done in linux with the MCSDK release.  But this will not be useful for us for this scenario.

    Is that possible for you to refer the POST in u-boot and suggest configuration of Digital loopback as stated in sprugv9d?

    Regards

    Rams

  • Rams,

    Yes, POST will perform an Ethernet loopback test. You can find the some information for loopback test at this thread.
    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/226597/798121.aspx#798121

    I am not familiar with u-boot, will check with team and let you know further help on the same.

  • Hi Pubesh,

    Thanks for the information.  I am unable to find information on loopback options other than PHY loopback.  It will be very useful to have and be able to test various loopback in POST as this will help in debugging custom hardware.

     We have a SGMII SGMII connection as described in SPRUGv9d  2.4.3.4 SGMII to SGMII with Forced Link Configuration.

    We see the link up in SGMII Status.  But we could not see transmit counters TXGOODFRAMES and RXGOODFRAMES or other error counters incrementing for the port.  

    How can we setup other loopback such as FIFO_LB in GbE Switch Control Register, loopback in MAC Control Register, loopback in SGMII Receive Configuration Register, loopback in SGMII Transmit Configuration Register.

    It would be nice to test these configuration on the EVM and compare the behaviour on custom hardware.

    Thanks

    Rams

  • Rams,

    I did not experiment various loopback test as per your case. But the test code avilable in MCSDK does not matching your sencerio.
    You can go through the KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem user guide for set the SGMII loopback using SGMII Control Register.
    You said that followed the below steps for Digital Loopback Configuration, what is the status for that? Did you get any error?

    • Clear to 0 the MR_AN_ENABLE bit in the SGMII_CONTROL Register
    • Write to 1 the RT_SOFT_RESET bit in the SOFT_RESET Register
    • Write to 1 the LOOPBACK bit in the SGMII_CONTROL Register
    • Write to zero the RT_SOFT_RESET bit in the SOFT_RESET Register
  • Rams,

    Yes, you can find the different loopback modes are supported:
    Digital Loopback Mode - MAC transmit to MAC receive. 
    FIFO Loopback Mode    - MAC receive to MAC transmit. 
    And SGMII or SerDes loopback mode (transmit to receive).

    The discussion held for keystone I device, see the below E2E post,
    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/343045/1199492.aspx#1199492
    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/226597/797928.aspx#797928

    Refer the evmc66x_phy.c file at : pdk_keystone2_3_00_03_15\packages\ti\platform\evmk2h\platform_lib\src

  • Rams,

    Did you check the E2E links as mentioned my previous post? Do you need further support, what is the status of getting loop-back code to work on the board? If you get the working setup or code for loopback , can you close this thread.

  • Hi Pubesh,

    Thanks!  We were able to use EMAC example from DSP to do loopbacks.

    Regards

    Rams