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CK and ADDR_CTRL Routing Specification on DM8148



Hi all,

I checked the DM8148 datasheet as follows portion. My query was CACLM only represented the distance of CPU to latest one DDR. That did not comprise the total length. The total length mean from CPU to all DDRs(4x 8bit or 2x 16bit per controller) trace. Was my view right?

B.R.

OC

  • OC,

    You are looking the part of the datasheet dedicated for the DDR2:

    8.13.4.1 DDR2 Routing Specifications
    8.13.4.2 DDR3 Routing Specifications

    In the DDR3 part we have more detailed information regarding CACLM, see section 8.13.4.2.4.13.1 CK and ADDR_CTRL Routing Specification, Figure 8-78, Figure 8-79 and Table 8-75.

    See also the below e2e threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/241051/843470.aspx#843470

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/156759.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/t/38241.aspx

    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/73164.aspx

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/62810.aspx

    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/263459.aspx

    Best regards,
    Pavel

  • Hi Pavel,

    Thanks so much for your reply.

    May I simply consult with you that "CK/ADDR_CTRL nominal trace length" is meant the longest distance from CPU to last one DDR?

    Because I traced DM8148EVM layout file that "Net path length" was large than "Total manhattan length". It seemed DM8148EVM did not follow the rules of datasheet. Please refer below information.

    =================================

    Net path length: 5016.0717 MIL

    Total manhattan length: 4337.5715 MIL

    =================================

    B.R.

    OC