Hi!
I have MCSDK 3.x HPC and SRIO over MPI example downloaded. I'm trying to enable SRIO interface but when I boot evm(66AK2H12) I get this error:
[ 12.728515] keystone-rapidio 2900000.rapidio: KeyStone RapidIO driver v1.2
[ 12.734141] keystone-rapidio 2900000.rapidio: initializing 5.00 Gbps interface with port configuration 15
[ 12.741970] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.750081] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.758192] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.766302] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.774412] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.782522] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.790632] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.798742] keystone-rapidio 2900000.rapidio: enabling packet forwarding to port 0 for DestID 0xffff - 0xffff
[ 12.807705] keystone-rapidio 2900000.rapidio: port 0 not ready
and finally
[ 233.438379] keystone-rapidio 2900000.rapidio: RIO port register timeout, port mask 0x1 not ready.
How to initialize srio port correctly? The EVM's srio interface is not physically connected, should it?
I have looked over sprugw1b - SRIO.pdf. I noticed that the keystone_rio driver gets timeout because keystone_rio_port_status(port, krio_priv) != 0. This is caused by AND operation between read-only bit[1] Port OK in register CSR n—SP(n)_ERR_STAT and RIO_PORT_N_ERR_STS_PORT_OK and result is not zero. Is this correct behaviour?
Should this bit Port OK get low by HW or how this is controlled? When something is connected to the port?
What is the case with internal loopback, does it need physical connection to get port working? I have tried to enable internal loopback to debug port and enabled LLB_EN bit in PLM_SP(n)_IMP_SPEC_CTL register but with no success.
br,
jv