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AM3517 DDR2 Data bus width

Prad
Expert 1125 points

Hi,

 

In the datasheet's features section, the Data bus width of SDRC Memory Controller

is written as 16 or 32-bit, but in the DDR2 Memory Controller feature described 

in page 105 states only about "Data bus width 16 bits".Is this a typo?

And I think there is some mistake in Schematics described in Figure 6-18 and Figure 6-19,

the figure is named as DDR2 Single-Memory for two memories, DDR2 Dual-Memory for a single connection.

 

Are two these two connections related to normal mode(Normal mode DDR 32 Bit) and Reduced package mode DDR 16 Bit

described in SPRUGR0 manual(page 700).

 

 

Thankyou. 

  • 0
    TI__Mastermind 41665 points

    Prad said:
    in page 105 states only about "Data bus width 16 bits".Is this a typo?

    This does appear to be a typo, the interface is certainly capable of 32 bit.

    Prad said:

    And I think there is some mistake in Schematics described in Figure 6-18 and Figure 6-19,

    the figure is named as DDR2 Single-Memory for two memories, DDR2 Dual-Memory for a single connection.

    This also looks to be a typo, the figure titles seem to be reversed.

    Prad said:

    Are two these two connections related to normal mode(Normal mode DDR 32 Bit) and Reduced package mode DDR 16 Bit

    described in SPRUGR0 manual(page 700).

    I do not believe so, the reduced package mode (FUNC_MODE_SEL bit)  seems to be a flag (as in read only boot pin setting) for specifying only x16 wide DDR, which would mean using one x16 wide memory as opposed to two for a x32 wide bus.

    To change the DDR2 bus itself to 16 bit mode regardless of the FUNC_MODE_SEL bit you would use SDRAM_CONFIG.REG_NARROW_MODE. My impression is that there is no configuration difference specific to between two x16 DDR2 chips and one x32 DDR2 chip, though this does not appear to be spelled out in the SPRUGR0 TRM.