question about C6678 pci express

Fabrizio Gualtieri

Other Parts Discussed in Thread: TMS320C6678

Hi,

we are testing a board on which is mounted a Texas Instruments DSP TMS320C6678.

In particular, the PCI express chain is the following :

PC -> PCI express cable -> test JIG (with a PLX PCI express to PCI bridge, PEX8112) -> Board (with a PLX PCI to PCI express bridge (PEX8112), a PLX PCI express switch (PEX8603) and two endpoints, a FPGA KINTEX7 and the DSP)

The FPGA and DSP link is 1x. In the FPGA we used the XILINX IP for PCI express Endpoint, whereas for DSP we started from the example project in the ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\PCIE_exampleProject path (this project uses the attached file).

The working procedure is that the FPGA and the DSP are running before the PC is powered on; the DSP is connected to XDS560 emulator for CCS interface.

When the PC is power on, the FPGA is properly enumerated, while the DSP isn’t.

We checked this situation, in particular the LTSSM_EN in COMMAND_STATUS register and the LTSSM_STATE in DEBUG0 register:

EVENT LTSSM_EN LTSSM_STATE

PC powered off 1 0x0 (DETECT_QUIET)

DSP running

PC turned on 1 0x11 (L0)

After about 1 second 1 0xD (RECOVERY_LOCK)

Next 0 0x0 (DETECT_QUIET)

I look forward to hearing from you

Best regards

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi Fabrizio,

I am not clear on your PCIe express interface, please provide the interface block diagram. For my understanding the DSP enumerated properly and then try to configure the PCIe as EP mode(I think the issue in this part). Please share your boot mode switch settings.

Have you configure the PCI Express module as two 1x links on your design? Please take a look at PCIe user guide (SPRUGS6D).

The PCI Express module supports a single bidirectional link interface (i.e., a single ingress port and a single egress port) with a maximum of two lanes width (×2)

The PCI Express module does not support for using ×2 link as two ×1 links.

Thanks,

0 Ganapathi Dhandapani95 over 10 years ago in reply to Ganapathi Dhandapani95

TI__Mastermind 28085 points

Hi ,

In the PCIe sample example two DSP EVMs are used to test the PCIe driver. EVM 1 is configured as a Root Complex and EVM 2 is configured as End Point.

Once the PCIe link is established, the following sequence of actions will happen:
* - EVM 1 sends data to EVM 2
* - EVM 2 waits to receive all the data
* - EVM 2 sends the data back to EVM 1
* - EVM 1 waits to receive all the data
* - EVM 1 verifies if the received data matches the sent data and declares.

This PCIe example code is not directly supported on your test setup. You need to modify the example project for your design.

Thanks,

0 Fabrizio Gualtieri over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 270 points

Hi,

in attached file you can see the PCI express interface block diagram.

we don't boot the DSP, but we use the CCS to execute the code (the DSP runs before the PC is turn on).

we configured the DSP as a 1x link (only a serdes is connected, the 2nd is unconnected); in the same attached file you can see the schematic detail

thanks in advance

PCIE_CHAIN.pdf

0 Ganapathi Dhandapani95 over 10 years ago in reply to Fabrizio Gualtieri

TI__Mastermind 28085 points

Hi Fabrizio,

Now i am clear on your PCIe Express interface.

Have you read my second reply?

The PCIE example project is supported for testing two DSP EVM. If you want more information, Please take a look at Readme.txt file(C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\pcie\example\sample\Readme.txt)

Thanks,

0 Fabrizio Gualtieri over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 270 points

hi,

i read the readme.txt file.

we don't have used this project directly; we took only the settings for the endpoint (naturally, we changed the lane width to 1x).

i attached the modified project file in my first post.

thanks

0 Fabrizio Gualtieri over 10 years ago in reply to Fabrizio Gualtieri

Intellectual 270 points

Hi,

i don't understand why in the page of the post is written "the question is answered".

thanks

0 Rogerio Almeida over 10 years ago in reply to Fabrizio Gualtieri

TI__Mastermind 26175 points

Fabrizio,

It looks like you have confirmed the answer was given to you was what you were looking for...Only the one that generates the post can do that...perhaps you have done it by mistake...

0 Fabrizio Gualtieri over 10 years ago in reply to Rogerio Almeida

Intellectual 270 points

Rogerio,

it's possible. what should I do to continue with this post?

thanks

0 Ganapathi Dhandapani95 over 10 years ago in reply to Fabrizio Gualtieri

TI__Mastermind 28085 points

Hi Fabrizio,

If you have any questions regarding PCIe configuration, please continue this thread.

I have reviewed your modified code, You added printRegisters() function only but, you commanded this function.

Please take the PCIe initialization part code from the example project and develop your own test code.

In PCIe example project - PCIe configured as EP and enable the link training to check the PCIe link and then link up the PCIe device.

Thanks,

0 Fabrizio Gualtieri over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 270 points

Hi,

we have done just that.

in attached file, you can see the our test code.

regards

Fabrizio

evmc66c_PCI.cpp

0 Ganapathi Dhandapani95 over 10 years ago in reply to Fabrizio Gualtieri

TI__Mastermind 28085 points

Hi Fabrizio,

I have reviewed your test code. It is fine for PCIe initialization(EP).

Thanks,

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question about C6678 pci express