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How to close the pipeline function?

C6747 

For test, how to invalidate  the pipeline? Or is it  impossible?

  • Hi Wang,

    Could you please bit elaborate your requirement.

  • Hi,

    I couldn't understand C6747 pipeline operation.

    I think it's a 11-stage pipeline and the pipeline executes 11 instuctions in one cycle.

    Could I configure some registers and make the pipeline execute only one instuction or only one instuction's one phase in one cycle.

  • Hi,

    Thanks for your update.

    Usually, pipelining techniques (DSP pipeline/Software pipelining) executes parallel processing of CPU instructons & it is designed for high CPU throughput & optimized instruction scheduling to ensure the full utilization of the pipeline. But as per your requirement which will execute only one instruction in one clock cycle would introduce more delay slots & CPU wait cycles before it can issue the next instruction. I mean, you need traditional scheduling which is a non-optimized instruction scheduling mechanism in which the CPU will consume more no. of clock cycles and proportionately, you will see a significant degradation in the CPU throughput.

    You could check the c6000 DSP optimization application report as below which will give you a better understanding on c6000 DSP pipeline & software pipeline techniques:

    http://www.ti.com/lit/an/sprabf2/sprabf2.pdf (see sections 2.2.2, 2.2.3, 2.3.1, 2.3.2)

    Also, please check sections 3.2, 3.3 & 3.4 in the c6000 optimizing compiler's user guide for software pipeline optimization as below:

    http://www.ti.com/lit/ug/spru187v/spru187v.pdf

    Thanks & regards,

    Sivaraj K

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  • Thank you for your answer. I'll try your sugestion.