C6745 375/456Mhz

Hello Hakeen,

Thanks for the post.

I hope you are sourcing 1.2V CVDD for 375 MHz version and 1.3V CVDD for 456 MHz version. In that case, Please check whether you configured the PLLC to get the SYSCLK1 as 456 MHZ for the board mounted with C6745*****4.

You have mentioned that you loaded the same program into both boards. I doubt, the program has different PLL configuration to operate at different frequencies.

Please refer C6745 TRM for chapter 7 for more details about PLLC configuration.

http://www.ti.com/lit/ug/spruh91b/spruh91b.pdf

Regards,
Senthil

Hi,

In addition to Senthil's point,

Please check out the below insights.

We load the program into our boards. One board mount C6745*****3. Another board mount C6745*****4.

Are you using CCS for loading program ?

How did you measure the performance?

You can have LED blink code for both boards and you can check the blinking time.

Have you modified the GEL file for 456MHz ?

I don't think that default gel file support 456MHz core freq.

Hi Senthil & Titus 

Thanks for your help.

My DSP part number  is C6745D****3 and C6745D****4 

Both are version D.

Device speed : 3 is 375MHz.  4 is 456MHz

I utilize CCS6 + JTAG to load program.

Check the sound output. Then, we could know whether there are too many instructions per seconds.....

According to datasheet (below image), SYSCLK1 should be DSP operation frequency.  Right ?

If PLLDV1 could control DSP operation frequency, I don't know which RATIO is for 375MHz ? Which RATIO is for 456MHz?  (Refer to below image)

Only changing PLLDIV1 is enough?  Or, should I change other registers??

I modify my own gel file. (Copied evmc6747_dsp.gel  in CCS6.  And change the PLL0 ......)

Hi Titus S.

Thx for the info.

I tried to trace Set_Core_456MHz() , Set_Core_372MHz() 

I found the gel file. 

OMAP-L138 should set core 300MHz in below way.

Set_Core_300MHz() {
device_PLL0(0,24,1,0,1,11,5);
GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:25MHz\n","Output",1,1,1);
}

Below is device_PLL0 function definition

device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {

For OMAP-L138,

Core_456MHz  CLKMODE=0, PLLM=18, POSTDIV=0, PLLDIV1=0, PLLDIV2=1, PLLDIV3=18, PLLDIV7=5

Core_372MHz　CLKMODE=0, PLLM=30, POSTDIV=1, PLLDIV1=0, PLLDIV2=1, PLLDIV3=18, PLLDIV7=5

Core_300MHz　CLKMODE=0, PLLM=24, POSTDIV=1, PLLDIV1=0, PLLDIV2=1, PLLDIV3=11, PLLDIV7=5

Below is C6747 Gel (CCS6 default)

Setup_PLL()
{
int i = 0;

/* DSP at 300MHz, EMIFs at 133MHz */
unsigned int DIV45_EN = 1;
unsigned int CLKMODE = 0;
unsigned int PLLM = 24;
unsigned int POSTDIV = 1;
unsigned int PLLDIV1 = 0;
unsigned int PLLDIV3 = 2;
unsigned int PLLDIV5 = 5;
unsigned int PLLDIV7 = 7;

C6747 300MHz  and OMAP-L137 300MHz  has different PLLDIV3 , PLLDIV7.  And C4745 don't set PLLDIV2.....

Although there are difference at same core frequency, I just set CLKMODE, PLLM and PLLDIV* of C6747 as same as OMAP-L138's.

It can't work.

Is there document explain these parameters more ?

The document "SPRS377E" don't explain the value of PLLDIV*,PLLM......

Hi Titus S. , Randy

Thx!

Found definition in spruh91b PDF

Hi Hakeen,

Thanks for your update.

Please ask us if you have any problem in PLL configurations for C6745 or any TI processors.