6657 PCIe boot laoder

Hi,

Ans1: No

Ans2: We recommend you to contact your local TI FAE/Sales for custom RBL support.

Ans3: BAR1 (Host PC configures the BAR1 as inbound to DSP core0 L2 memory)

Ans4:

a. Refer following link for DSP BAR configuration - http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/204910.aspx

b. Refer Linux host loader code (pciedemo.c).

Ans5: It runs on L2 SRAM, please refer pushdata() in pciedemo.c

Ans6: In pcidemo example, BAR0 access PCIe Config Reg, BAR1 access the L2SRAM of DSP Core0, BAR2 access the MSMC of DSP and BAR3 access the DDR of DSP.

What command would you like to pass to DSP via PCIe?

Thanks,

Thanks,

Q1. When the DSP has booted from an image via PCIe and the DSP is running, Is it possible to calculate the checksum on the image file? how can the DSP reach each byte of the image which is now copied to L2 SRAM while running the image program the from the same place,  L2 SRAM ?

Q2. I got an answer that RBL can't be changed.

Q3 .After the Host (PC) sent the image file to BAR1. How does the DSP knows that image transmit has been completed and starts executing the image program?

In order to start DSP program execution : Does the Host has to send a reset command via the PCIe or to change the Magic_Address ?

From which address the program of the DSP starts to run? from address '0' ? or from the value of Magic_address(4 first byte of boot code) ? 

Q4 : How can I change the BAR mapping during DSP run ? 

for example : I want to change to this mapping : 

BAR     REGION      FUNCTION MEMORY         SPACE     SIZE

BAR 0                     CONFIGURATION 0
BAR 1                     NOT IN USE
BAR 2 REGION 1    SHARED MEMORY           0C000000    1MB
BAR 3 REGION 2    L2 CORE 0 MEMORY        10800000     1MB
BAR 4 REGION 3    L2 CORE 1 MEMORY        11800000     1MB
BAR 5 REGION 4    PCIe CONFIG/DDR             21800000    32KB/2GB

Is it possible ?

Q5. I would like to pass simple command from the PC to the DSP (1-2 bytes) via the PCIe and return status from DSP to PC

for example : turn on GPIO LEDS.

To which BAR should I send such commands ?

How the DSP knows that a command has been recieved?

How the PC knows that a status is answered ?

Thank you very much,

Ivgeni.

Hi,

Q1. Please explain : "The changing of L2SRAM data will corrupt the PCIe booting". 

I want to add a checksum value to the image which sent over the PCIe and check it after PCIe booting is completed.

Q3. Please explain : Does the Host has to send any command after sending the image file to BAR1 ?

Q4. I don't understand : 

When I  want to boot over the PCIe, I set the switches on the EVM board to PCIe boot state.

in that state, EVM's boot loader is RBL. The BAR configuration Is determined in EVM's Power On Reset( in RBL code)

How modifying the IBL can change the BAR configuration ?

Q5. I am writing such application . I just can't find answers for the following questions :

a. To which BAR should I send such commands ?

b. How the DSP knows that a command has been received?

c. How the PC knows that a status is answered ?

Thank you very much,

Ivgeni

Hi,

Please go through the demo project and run them. From your questions, I understand that you are not running the demo. 

A3. Yes.

A4. Are you able run the pciedemo successfully?

From my understanding, the demo program uses IBL for PCIe BAR configuration. 

A5.

a. You DSP image file should decode the commands send by the host and process it.

b. Your DSP image file should poll for the data from host or interrupt. The demo is based on MSI interrupt.

c. Please send the acknowledgment back from dsp to pc as needed.

Thanks.

HI,

Ther demo projects arelocated in  : 

ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie    ?

Q3.  After sending the image file to BAR1, which command the PC should send to the DSP in order to activate the program?

Q4. I am running from windows 7, so I can't run pciedemo (it is for Linux).

I am booting from PCIe(I set switches to PCIe boot) . I don't think I can use the IBL in the boot process for PCIe BAR configuration.

Q5. b. which "demo" ?

Q6. On a new 6657 DSP, how the configuration between BARs and memory is configured ?

What is the default BAR to memory map on the DSP ?

Thanks,

Ivgeni.

Hi,

Q4. I am booting in pcie with RBL. What is the bar to memory map in the DSP ? In which code can I find it ?

I have only the code for IBL which doesn't help me.

Thanks.

Hi Ivgeni,

Please share your boot mode switch settings?

Take a look at below link:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/309591/1096046.aspx#1096046

Thanks,

Boot Mode
ROM PCIE Boot

DIP SW3
(off, on, on, off, on, on, on, on)
(Pin1, 2, 3, 4, 5, 6, 7, 8)

DIP SW5
(on, on, on, off, off, on, on, on)
(Pin1, 2, 3, 4, 5, 6, 7, 8)

Hi Ivgeni,

IBL code is required for this boot mode. You need to flash the IBL binnary to EEPROM address 0x51.

Please take a look at below thread:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/203172/1055080.aspx#1055080

You modified the BAR configuration in IBL source code.

Thanks,

In this mode : ROM PCIE Boot, I am booting from IBL, from EEprom ?

Please refer the above link, that thread have detailed information. 

Hi Ganapathi,

I looked at the BAR configuration in the IBL code.

I understand that the IBL sets the start address and the BAR size of each BAR.

My question : 

When I write from PC directly to desired address, Do I need to look at the IBL's BAR configuration?

for example :

for "inbound" protocol : 

a. I am writing from the PC to the virtual address of the PCIe with an offset of  0x00800000 when I want to write to Local L2 SRAM on the DSP.

b. I am writing from the PC to the virtual address of the PCIe with an offset of  0x80000000 when I want to write to DDR3 EMIF data on the DSP.

For outbound "protocol", when I want to write data from DSP to PC:

I am writing from the DSP to PCIe data (0x60000000) address and the PC reads from virtual address of the PCIe  with offset of 0x60000000.

Am I correct ?

Thanks,

Ivgeni.

Hi Ivgeni,

Your understanding is correct.

In pciedemo.c all BAR's are configured as INBOUND on DSP side. This demo host PC write/read the data to DSP memory. So that only all the BARs are configured as IB. If you want to write DSP to PC memory, you need to configure any one BAR as OUTBOUND on DSP side.

Thanks,