Hello,
I have a question about DDR3A data access from CortexA15 in 66AK2H12/06.
66AK2H memory mapping is following:
- DDR3A data area can be accessed by DSP core using XMC.
- How can the DDR3A data be accessed by ARM?
I guess that ARM core can access DDR3A data via MMU.
Is that correct?
Best regards, RY