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SPI INTERFACE BETWEEN DSP AND FPGA

NITHIN BOJJA
Intellectual 505 points
Other Parts Discussed in Thread: TMS320C6678

Hi,

   We have designed a custom design board taking the reference of  TMS320C6678 EVM Board for TI schematics. We want to implement SPI interface between DSP and FPGA. First I want to understand the working of SPI interface between DSP and FPGA on 6678 EVM board. We have 6678 EVM board with us. Can you tell me which code, we have to study for this (is it platform_test). I guess we have to select chip select  CS1 for DSP FPGA SPI interface. How to change this? (chip select 0 is selected default value is what i understood). Please help me on this so that we can successfully implement SPI interface on our custom board.

                                                                                                                                                  Thanks and Regards,

                                                                                                                                                       Nithin B.

  • 0
    TI__Guru* 81335 points

    Hi Nithin,

    We are working on your query. We will answer your query. Thank you for your patience.

  • 0 in reply to Raja
    Intellectual 505 points

    Hi,

       Thanks for the  reply. I will be waiting for your assistance.

                                                                       Thanks and Regards,

                                                                                   Nithin B

  • 0 in reply to Raja
    Prodigy 100 points

    Hi Rajasekaran,

    I am on the same team with Nithin working on the fpga side. I have gone through the FPGA - DSP SPI interface verilog code (dsp_spi.v) provided with the EVM revision3. There are a few doubts:

    1) I am not able to find any description of the signals used between the FPGA spi module and FPGA user logic (i.e. the functions of interfacing signals like addr, rdy, wr_event_cng, etc. are not clearly stated). Where can we find the description of those interfacing signals?

    2) Do you guys have any timing diagram regarding the SPI interface other than the one given in EVM documents? In the EVM docs, it only talks about the four SPI signals. What we need is the timing diagram that includes the interface between the SPI interface module and FPGA user logic. If I could get this timing diagram, many doubts would be cleared.

    Warm Regards,

    Binayak.

  • 0 in reply to Binayak Shrestha
    TI__Mastermind 42545 points

    Hi Binayak,

    The FPGA code used on the EVM was developed by Advantech. The sample verilog code was provided to give you the basic functionality of the FPGA but we do not provide all the information needed to build the FPGA. The signals you described are the internal signals generated by Advantech to operate the SPI interface. We don't have any additional detail on the signals. I am sure that you could set up a simulation using the timing diagram for the four external SPI signals as a source to determine the function of the other internal signals in the dsp_spi module. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 505 points

    Hi,

       Thanks for the reply. We will first understand the spi interface on EVM board itself. The  fpga code will be anyway flashed into FPGA in EVM board. In platform_test project, I have selected  CS 1.(spi_claim(SPI_FPGA_CS, SPI_MAX_FREQ);). By this function spi initialization part is over and now i have to do data transfer  (i guess). What additional thing has to be done on the code because there are functions for FPGA READ/WRITE in the code but I feel I have to enable them. Can you suggest me what changes I have to do so that i can be able to send data from dsp to fpga in evm board.

    Regards,

    Nithin B

  • 0 in reply to NITHIN BOJJA
    TI__Mastermind 42545 points

    Hi Nithin,

    Unfortunately, I am not a software expert. I suggest you post the software questions into a different thread so that they can be assigned to the proper support person. 

    One additional note on the FPGA. The FPGA on the EVM was not intended to be a test platform for customer built E2E code. Changing the FPGA programming may cause portions of the EVM to operate incorrectly. We cannot guarantee proper operation of the EVM unless the FPGA is programmed with the code that is delivered with the board. 

    Regards, Bill