Hi, recently I encounter a cache-related problem. The application scenario is assumed as follow:
Presupposition 1) two core2, e.g. core#0 and core#1 are used. In every core, all L1D space is configured as cache.
Presupposition 2) an array char x[256] is defined in MCSM memory. Its starting address is 0x0c000000. Meanwhile, x[0] to x[32] will be accessed by core#0 and x[33] to x[255] by core#1. The accesses to x are simultaneous since core#0 and core#1 are running concurrently.
Presupposition 3) the memory allocation is fixed in two cores.
In order to maintain the cache coherence, the function CACHE_wbL1d(Address, ByteCnt, WAIT) is used. But in core#0, the Address(i.e. 0x0c000000) is 64-Bytes aligned but the ByteCnt(i.e. 32) is not 64-Bytes. In core#0, the Address(i.e. 0x0c000020) and ByteCnt(i.e. 224) are both not 64-Bytes aligned.
The address and length alignment can not be reached through memory reallocation because of Presupposition 3), my solution is:
For core#0, since the ByteCnt is not 64-Bytes, therefore, more bytes, i.e. 64-Bytes is actually written back and CACHE_wbL1d(0x0c000000, 64, WAIT) is used. But more bytes are written back.
For core#1, since the Address and ByteCnt parameters are both not 64-Bytes aligned, therefore, the Address reduces to 0x0c000000 and ByteCnt incease to 256 and CACHE_wbL1d(0x0c000000, 256, WAIT) is used. But more bytes are written back.
My question is that whether my solution is correct or not? If not, how to solve the problem?
In my understanding, if the written back of core#0 is first, perhaps the date in x[0] to x[32] written by core#0 will be wiped off by core#1 and vice versa. Is my understand correct or not.
Thank you for your kind help !
