Hi,
I was trying to configure OMAP3530 I2C in FIFO interrupt mode as per the instruction given in the Datasheet. But Iam not getting any interrupt, for any states, even for start condition detected. While reading the status register I found XDR, BB, XUDF bits are always getting set. Even after wiriting 1 to the XDR bit in I2C_STAT, this status is not getting cleared.
This is how my sequence follows.
I2c_Init:
1. configure I2C pads SCL & SDA
2. enable I2C fclk & iclk
3. disable all interrupts
4. disable I2C_Buf
5. disable system test mode
6. disable I2C controller
7. set soft reset I2C_SYSC -> 0x02
8. enable I2C controller
9. wait for reset to complete(check SYSS_RDONE bit)
10. disable I2C controller
11. read I2C_BUFSTAT of the I2C controller to get fifo depth
12. load I2c_buf with (fifo depth/2)-1 & set txfifo_clr & rxfifo_clr bit
13. enable I2C controller
14. enable xrdy,rrdy,xdr,rdr,al,adry,nack,stc interrupts
15. check for bus busy status, if bus is busy, generate stop
INTC_init:
1. set priority 6, 7,8 for I2C1,2,&3 respectively.
2. clear bit 24,25,29 in INTCPS_MIR1 register
I2C_write:
1. load psc value - 0x0009
2. load scll value - 0x0005
3. load sclh value - 0x0007
4. load 0xffff to clear I2C_stat register
5. read I2C_stat register & check for BB to clear.
6. load 0xffff to clear I2C_stat register
7. load slave addr in I2C_SA register
8. load 2 in I2C_CNT
9. read I2C_BUFSTAT of the I2C controller to get fifo depth
10. load I2c_buf & set txfifo_clr & rxfifo_clr bit
11. clear OPMOde(F/S mode), XSA(7bit address) bits and set ->I2C_CON_EN,MST, TRX, STP, STT bits
Can any one help me in testing the I2C using FIFO Interrupt mode by looking the above sequence.
Thanks in advance.
Regards,
Yuvaraj.V
