Reg.RMII interface

Hi Ibram,

The RMII REF_CLK input signal of AM335X must be connected to an external low-jitter 50MHz clock source. The CLKOUT pin of TLK110 provides a 50MHz output in RMII mode, but I cannot say whether it fulfills the requirements listed in section 7.6.1.3 of the AM335X Datasheet, Rev. G.

Biser Gatchev-XID said:

Hi Ibram,

The RMII REF_CLK input signal of AM335X must be connected to an external low-jitter 50MHz clock source. The CLKOUT pin of TLK110 provides a 50MHz output in RMII mode, but I cannot say whether it fulfills the requirements listed in section 7.6.1.3 of the AM335X Datasheet, Rev. G.

The TLK110 cannot source the RMII 50MHz clock:

I have received verification from the TLK team that the TLK110 clock-out is not intended to be used as the RMII interface clock. An external 50MHz oscillator would be required for RMII operation of this PHY.

http://e2e.ti.com/support/arm/sitara_arm/f/791/p/214462/1092561.aspx#1092561

Hi,

I have followed below interface. I have shared the clock source between TLK110 and AM3359(H16-RMII2 ref clk). Is that OK?

Regards,

Ibram

Yes, this is correct.

Hi Biser,

But we do not see any activity on this interface.

we measured the clock, it is showing 50MHz. In the above hardware connection, we have ingored the optional ones.

anything suggestion on this would help us a lot.

Regards,

Ibram

Hi Ibram,

The required connections are shown in Figure 14-4 and Table 14-6 in the AM335X TRM Rev. K. Do you have the MDIO interface connected? What software do you use?

Hi Biser,

Yes MDIO is connected. we are using generic driver from 5.07 BSP version. This driver works for us with MII interface using Micrel PHY.

Regards,

Ibram

Does the PHY get detected by MDIO? 5.07 SDK is rather old, have you tried with 6.00 at least?

Hi Biser,

we have not tried with 6.00. but PHY is getting detected.

Regards,

Ibram

I suppose you have also made the correct pinmux settings?

Hi Biser,

yese we have made the correct pin mux.

Below are pins used for RMII interface:

R14 - TX_D1;

V15 - TX_D0;

R13 - TX_EN;

T16 -  RX_D1;

V17 - RX_D0;

U17 - RX_ER;

T13 - CRS_DV;

H16 - Ref_CLK;

M18 - MDIO_CLK;

M17 - MDIO_Data

Please let me know if this is ok and we have also checked that these pins are getting conflict with other interface.

Regards,

Ibram

There are no pinmux conflicts. Can you post your pinmux settings?

Hi,

i will not be able to share pin mux settings because of some internal restriction.

we have checked with software, we didnt see any conflicts.If you need any particular interface then i can you those manually.

Regards,

Ibram

OK, check then that you have RX enabled on all input signals. Also check Advisory 1.0.16 in the AM335X Errata Rev. F.

Hi Biser,

How to check RX enable?

we are giving external clock source whichmeans we are following the advisory in eratta.

Regards,

Ibram

Ibram sahibu said:

How to check RX enable?

In the pinmux settings.

Ibram sahibu said:

we are giving external clock source whichmeans we are following the advisory in eratta.

The errata says:

RMII1_REFCLK can be configured to input mode by setting bit 6 of the GMII_SEL register to 1b. RMII2_REFCLK can be configured to input mode by setting bit 7 of the GMII_SEL register to 1b.

Hi Biser,

There is no RX enable in the RMII interface as per the datasheet. so which one you are referring to?

For RMII2_REFCLK after setting bit 7 in the GMII_SEL register, (As per errata) we are unable to detect PHY on MDIO Bus. However without following eratta we are able to detect PHY.

This seems to be unusual behaviour. Do you have any suggestions?

Regards,

Ibram 

Ibram sahibu said:

There is no RX enable in the RMII interface as per the datasheet. so which one you are referring to?

I am talking about pad configuration registers. See section 9.3.1.50 in the AM335X TRM Rev. K.

Ibram sahibu said:

For RMII2_REFCLK after setting bit 7 in the GMII_SEL register, (As per errata) we are unable to detect PHY on MDIO Bus. However without following eratta we are able to detect PHY.

This is stange indeed. No idea what is happening.

This is very odd...I'm not sure what one would have to do with the other as MDIO and RMII are completely separate interfaces. Can you scope the MDC and see if the clock stops when you set RMII2_REFCLK?

Hi,

Still we didnt bring up the RMII interface. we need your help desperately. I have attaced the schematic for your reference. please let me know your comment in it.

0830.BWIR_RMII.pdf

I have measured Ref clk it shows 50MHz. The PHY is also getting detected but we dont see any activity in the interface.

Regards,

Ibram

JTAG TRST is active (Low) while TLK110 has internal pull-up. Should be benign but who knows..

MII_COL (pin42) has internal pull-up. Which Phy Addr do you want to use? Yes, the driver scans MDIO but as I remember I had problems until had set PHYADDR to "0". 

Yes it has internal pull up but the recommendation is to use external pulldown and system will drives it to high overridding the resistor.

However we are not using JTAG at the moment.

Regards,

Ibram