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Why there is no CACHE_L2 in my DSP/BIOS config file?

Jack Lee1
Prodigy 70 points

whe i create a dsp/bios configure file for my ccs5.5 program.

in the MEM module,there is no CACHE_L2 as in the following figure

i want insert the CACHE_L2 to the MEM ,but there is a erro message as the following figure.

can somebody tell me why?

 

  • 0
    TI__Guru** 116100 points

    Hi Jack,

    Which examples are your trying to run ?

    TI examples or own ?

    The L2 memory may be configured to run a app.

    Please check your linker command ".cmd" file.

  • 0 in reply to Titusrathinaraj Stalin
    TI__Guru* 84110 points

    Jack,

    This question should be posted in the TI-RTOS Forum instead of this C6000 Single Core DSP Forum.

    You have allocated the full size of the L2 memory range as IRAM so there is no space remaining for cache.

    CACHE_L2 is automatically created by DSP/BIOS based on your configuration settings. Find the location in the configuration settings where you define the size of L2 RAM and L2 cache, and then DSP/BIOS will take care of the allocation for you.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 70 points

    after  creating a "hello world"  CCS project ,I  Create a DSP/BIOS v5.x Configuration File.

    In the MEM, there are only  IRAM and SDRAM ,I can‘t  find CACHE_L2 in there

    After i compile it ,there is no CACHE_L2 in the  cmd file or map file.

    when i insert the CACHE_L2 ,there is the error message :Object CACHE_L2 already exists!

  • 0 in reply to Jack Lee1
    TI__Guru* 84110 points

    A moderator will move this thread to the TI-RTOS forum.

  • 0 in reply to RandyP
    TI__Guru* 84110 points

    It is possible that CCSv5 does not create or use the CACHE_L2 section. It is not needed for anything other than preventing you from allocation anything in that same space. You should never use this section, if it does exist, other than to see that it does exist.

    The CACHE_L2 section is not needed for proper cache use, only for documentation at the project level.

    Regards,
    RandyP

  • 0 in reply to Jack Lee1
    TI__Mastermind 32475 points

    Just adding to what the other TI guys have said.

    CACHE_L2 is an internal MEM segment created to prevent you from placing any code or data into the part of L2 that is Cache.  You cannot create a MEM segment with the same name.  You won't see it because you already have the whole L2 RAM segment specified as RAM in your IRAM segment.  Hope that makes sense.

    Judah

  • 0 in reply to judahvang
    Prodigy 70 points

    judahvang said:

    Just adding to what the other TI guys have said.

    CACHE_L2 is an internal MEM segment created to prevent you from placing any code or data into the part of L2 that is Cache.  You cannot create a MEM segment with the same name.  You won't see it because you already have the whole L2 RAM segment specified as RAM in your IRAM segment.  Hope that makes sense.

    Judah

    How can i  split some space in the  whole L2 RAM as CACHE_L2,and how should i configure the DSP/BIOS?  

  • 0 in reply to Jack Lee1
    TI__Mastermind 32475 points

    Hi,

    Yes, its easy to do that.  If you right click "Global Settings" and select "properties" and select "64Plus" tab you will see the options to set the size of your caches.  So first decided on what cache size you want.

    Next if you want to split up the L2 Memory, just modify the base/szie of "IRAM" in MEM by:
    Right click "IRAM" and select "Properties".  Then change base and/or len and click "OK".

    Next Right Click "MEM" and choose "Insert MEM".  This will create a new MEM object.  YOu can now change the new MEM object with the base and len that you want.  Here's a pic of me adding a new MEM0 with base/len.

    Judah