Clock to UART AM3703

Hi,

You are correct about the UART functional clocks - they are fixed at 48MHz. These clocks are sourced and gated in the PRCM module of the processor - CORE_48M_FCLK for UART1/2 and PER_48M_FCLK for UART3/4. The respective clocks are generated by DPLL3 and DPLL4.

Yes, UART1/2 are the ports I care about...so CORE_48M_FCLK is the one that matters to me.

However, the docs make it look like DPLL4 generates CORE_48M_FCLK, not DPLL3 as you suggested.

How does one set up the correct PLL to generate 48MHz or does the designer not need to touch anything at all?

(I'm trying to hunt down what *might* be a baud rate error so I am suspicious that the "48MHz" might not be 48Mhz.)

In AM37X PLL initialization is done by the ROM code. See section 26.4.4.2 in the AM37X TRM Rev. R for details.

I'm new to this part so I would like some background information

1) The so-called "ROM code" is built in to the chip by TI and is not something the end user modifies, correct?
2) The settings to create the peripheral 48MHz clock are made automatically by the ROM code  - the ROM code measures the CPU's input clock frequency somehow and sets up registers based on that measurement, correct?

Regards,
Mike