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Four DMA transfers simultaneously

Hi,


I’m going to use 320C6748 DSP for my new board design.

In the 320C6748 DSP data sheet, DMA features are written as follows.
Enhanced Direct Memory Access Controller 3 (EDMA3)
– 2 Channel Controllers DDR2 Interfaces
– 3 Transfer Controllers
– 64 Independent DMA Channels
– Programmable Transfer Burst Size

But I’m not sure if 320C6748 supports 4 channel DMA simultaneously, like this.

It is possible for 320C6748 to handle 4 DMA transfers simultaneously?
If so, tell me how to use please

  • JungBai Park,

    What is the interface you will use between the FPGA and the DSP to physically transfer the data? Will this be the EMIF for parallel data transfer or a serial port or four serial ports, or something else?

    What is the data size and data rate from your ADCs?

    Regards,
    RandyP

  • Dear RandyP,

    The interface will be EMIF.

    ADC will run at up to 200K samples/sec with 16bit width.

    Each DMA channel of FPGA will be mapped to a unique address.

    The FPGA address can be fixed (not incresed by read operation), right?

    Thanks.

  • JungBai Park,

    JungBai Park said:
    The interface will be EMIF.

    Since the FPGA is interfacing to a single 16-bit-wide EMIF bus, it cannot deliver all 4 samples simultaneously. The technical answer to your question, as it was asked, is: no, the 4 samples cannot be read simultaneously with one EMIF interface.

    JungBai Park said:
    ADC will run at up to 200K samples/sec with 16bit width.

    The question you really want to ask, in my opinion, is whether the DSP can read the 4 samples fast enough. There are two criteria for "fast enough": required DSP output latency (delivering the results of the DSP's calculations) and real-time constraints. You have to determine the required output latency from your application's goals, such as motor control stability, echo detection/cancellation, or data delivery requirements.

    You can determine meeting or exceeding the real-time constraint by using the speeds at which the EMIF will run and comparing that to the speeds at which the samples are taken. You set the EMIF clock rate. Assume a best-case of 4 EMIF clock cycles per 16-bit sample, but allow for board parameters and FPGA design parameters which could increase the minimum number of EMIF clock cycles needed. If that time is much faster than the 200K*4 samples per second to be read, then the second constraint is met.

    JungBai Park said:

    Each DMA channel of FPGA will be mapped to a unique address.

    The FPGA address can be fixed (not increased by read operation), right?

    You can used fixed addresses. You tell the DSP or EDMA3 to read from a given address or addresses so you can determine how the interface is operated.

    For optimum performance with the DSP, allow the 4 samples to be read from a sequence of 4 consecutive addresses. This will allow the EDMA3 to read all 4 samples in a single burst. It should be acceptable for the FPGA to implement this as a FIFO read port that ignores the lower 2 EMIF address bits for the FIFO. Or the FIFO can fully decode the 4 separate addresses as 4 sequential locations to achieve the same result with a little more flexibility, such as reading only 1 of the 4 samples for testing purposes.

    Regards,
    RandyP

  • Thank you very much, RandyP.