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Driving Clocks to a 66AK2H06 before CVDD is Valid

Mark Cear
Prodigy 100 points

Other Parts Discussed in Thread: 66AK2H06

I'm working on a new design and I'm copying a portion of an old design, and I'm looking at the clock inputs to the Keystone II 66AK2H06 on the existing design.  I believe that the clocks are being driven in to the device before CVDD is valid (not positive but it looks to be true).  But the existing design works fine and there's been no damage to the processor.

One thing I noticed is that all of the clock inputs are AC-coupled with 0.1 uF capacitors.  Are the capacitors providing protection to the device?  Or stated another way, if AC-coupling is used on the clock inputs to the uP, is it OK to drive the clocks high, or active, before CVDD is valid?

Thanks.

 

  • 0
    TI__Guru* 81335 points

    Hi Mark,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    Please follow guidance provided in Keystone Hardware Design Guide SPRABI2.

    I have requested experts to answer your query. Thank you for your patience.

  • 0
    TI__Mastermind 42545 points

    Hi Mark,

    Others have asked this question in the past as well. Some differential drivers can disable the outputs and some will drive one leg high and the other leg low at a constant level. As long as the clock signal is not toggling before CVDD is present, either of these scenarios is acceptable.

    Regards, Bill