C6657 PCIe internal trace length on the differential pair

Daisuke Maeda

Guru 20245 points

For the differential pair of C6657 PCIe, is it required to consider the length mismatch in the package? If so, please let me know the internal trace length.

For TUSB73x0, the internal length is considered: http://e2e.ti.com/support/interface/digital_interface/f/130/t/353587.aspx

Best regards,

Daisuke

over 11 years ago

0 Bill Taboada over 11 years ago

TI__Mastermind 42545 points

Hi Daisuke,

The length differential on the internal substrate has been accounted for in the routing requirements. You don't need to consider that differential in your length calculations.

Regards, Bill

0 Daisuke Maeda over 11 years ago in reply to Bill Taboada

Guru 20245 points

Hi Bill,

Thank you for your reply.

For the routing requirements, are following references enough?

Hardware Design Guide for KeyStone Devices (Rev. C)
http://www.ti.com/lit/an/sprabi2c/sprabi2c.pdf
10 Routing Guidelines

SerDes Implementation Guidelines for KeyStone I Devices
http://www.ti.com/lit/an/sprabc1/sprabc1.pdf
2 General PCB Routing Recommendations
7.2 Recommended SerDes PCB Layout Constraints

Clocking Design Guide for KeyStone Devices
http://www.ti.com/lit/an/sprabi4/sprabi4.pdf
6 Assembly Considerations

Best regards,

Daisuke

0 Bill Taboada over 11 years ago in reply to Daisuke Maeda

TI__Mastermind 42545 points

Hi Daisuke,

These are the correct references. The Hardware Design Guide points to the Serdes Implementation guidelines which have specific routing guidelines for the PCIE serdes signals. The clocking design guidelines provides specific information on selecting and routing the reference clock signals and not the serdes signals.

Regards, Bill

0 Daisuke Maeda over 11 years ago in reply to Bill Taboada

Guru 20245 points

Hi Bill,

Thank you for your reply.

Best regards,

Daisuke

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C6657 PCIe internal trace length on the differential pair