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6678 EMIF BetweenFPGA andDSP

tv sagar
Intellectual 300 points

Hi,

In our custom board we are using EMIF interface between 6678 DSP and FPGA. The clock source to both devices are different, what i mean to say is we have a crystal on the board which through clock synthesizer gives clock input to the DSP and FPGA has its own crystal and FPGA is using this clock. If I use different clocks there will be any synchronization issues? when i am reading data from FPGA to DSP i am some times reading same data twice in the DSP. Is this because FPGA and DSP has different clock? Any suggestion is appreciated.

Thank You,

VSagar

  • 0
    TI__Mastermind 42545 points

    Hi VSagar,

    The EMIF16 interface in the KeyStone devices is completely asynchronous. Even if you are using the same clock for both the KeyStone device and the FPGA, you have to treat that interface as asynchronous and calculate your timing based on the setup, strobe and hold times in the data manual. You will have to program the FPGA to read and write the data based on the timing that you program into the EMIF16 configuration registers.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 300 points

    Hi Bill Thanks for the reply, I am just creating the RAM in FPGA and filling the RAM with some data using FPGA clock and sending signal to DSP that data is available to read. When i am reading the data in the DSP some times i am reading the same data, am I doing right. Please suggest.

    Thank You,

    VSagar

  • 0 in reply to tv sagar
    TI__Mastermind 42545 points

    Hi VSagar,

    FPGAs are, generally, synchronous devices. How is your FPGA programmed to respond to the EMIF16 signals? Do you have a synchronous state machine that responds to the chip enable? Have you captured any of the waveforms with the access fails?

    Regards, Bill