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AM335X NOR flash - 256MB issue

Sankar S
Intellectual 405 points

Here is the details of the hardware that we have:

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/334694.aspx?pi301021=1

(silicon version used in 2.1)

 If we try to access the 128MB NOR flash then, there is no issues seen. The NOR flash can be write/read. But, when we try to access beyond 128MB (last bit of NOR flash A26 is not getting asserted), the pin connected to NOR flash from AM335X is GPMC_A11 and the corresponding PIN MUX register value (@ address 0x44e1086c which is conf_gpmc_a11) is 0x20. (Also tried with 0x24)

 I don’t think, there is no other register other than the pin mux register that need to be looked since the flash access of 128MB is okay. Please advice any other possibility to try.

 Please confirm whether the GPMC pin Muxing as in Table 7-5 of latest TRM (j) is validated in any of the designs and found to be working (GPMC_A[27])

  • 0
    TI__Mastermind 25235 points

    Hi Sankar,

    I have forwarded your question to the Sitara factory team.

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Intellectual 405 points

    Hi Miroslav,

    When will I be getting an update on this.. please.

  • 0 in reply to Sankar S
    TI__Mastermind 25235 points

    I'm sorry, but I can't help further. Our hardware engineer is on vacation.

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    TI__Guru**** 393215 points

    Hi Sankar,

    Can you please post a schematic (PDF file) of your connections between the AM335X GPMC and the NOR Flash?

  • 0 in reply to Biser Gatchev-XID
    Intellectual 405 points

    Hi Biser, can you please share your email address so that I can email you? 

  • 0 in reply to Sankar S
    TI__Guru**** 393215 points

    I have sent you a friend request. My e-mail is in it.

  • 0 in reply to Biser Gatchev-XID
    TI__Guru**** 393215 points

    I can't see anything wrong on the schematics. Can you post the GPMC registers settings?

  • 0 in reply to Biser Gatchev-XID
    Intellectual 405 points

    hi Biser, please see the dump. The CONFIG7 register is written with 0x50; when we tried to use 0x48 then, the board reboot because of data abort. Also, we had tried to stimulate the same via CCS and could see the same issue.

    U-Boot# md 0x50000000
    50000000: 00000060 00000000 00000000 00000000    `...............
    50000010: 00000008 00000001 00000000 00000000    ................
    50000020: 00000000 00000000 00000000 00000000    ................
    50000030: 00000000 00000000 00000000 00000000    ................
    50000040: 00001ff0 00000000 00000000 00000000    ................
    50000050: 00000200 00000101 00000000 00000000    ................
    50000060: 00001210 00101000 00030301 10041004    ................
    50000070: 000c1010 08070280 00000050 ee010f10    ........P.......
    50000080: e59f0300 ee0c0f10 00000000 00000000    ................
    50000090: 00001000 00101001 22060514 10057016    ...........".p..
    500000a0: 010f1111 8f070000 00000f00data abort

  • 0 in reply to Sankar S
    TI__Guru**** 393215 points

    Please see Table 2-1 on page 175 of the AM335X TRM Rev. K, especially Note (1) below the table.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 405 points

    Biser, there is no issue when i configure the CONFIG7 register with 0x848 and try to access 128MB with base address as 0x0800_0000; if I try to configure the CONFIG7 as 0x48 then the reset issue occur. The note is valid only for CONFIG7 register value programmed to 0x40 I believe.

  • 0 in reply to Sankar S
    TI__Guru**** 393215 points

    Hi Sankar,

    I have feedback from the factory team, confirming that 256MB CS size is working for 16-bit AD mux mode. Here is the description:

    "AM335x GPMC 16bit Multiplexed NOR Flash 256MB access should be working now since I have confirmed the GPMC_A27 pin(GPMC_A11 Mux mode 4) functionality for the 128MB+ access.  

    The GPMC_A27 pin is going to a weird state when configured for the Mux mode (based on the SYSBOOT[11:10] setting) by the Boot ROM at power on reset. Hence configuring again to the Mux mode the GPMC_A27 is not getting asserted. This needs a workaround of setting the GPMC_CONFIG1_0 = 0x0  and then configuring for the Mux mode GPMC_CONFIG1_0 = 0x00001200. After this sequence the GPMC_A27 assertion is happening as expected for the 128MB+ location.
     
    I have verified this on a AM335x ICE EVM v2.1A and accessing through the CCS Memory window.
     
    GPMC_CONFIG1_0 = 0x00001200 – 16bit Multiplexed mode
    GPMC_CONFIG7_0 = 0x00000050 – Base Address 0x10000000, 256MB CS# size
    Memory location tested for the GPMC_A27 function:   0x18000000
     
    Please try this on your side and provide your feedback."
  • 0 in reply to Biser Gatchev-XID
    Intellectual 405 points

    Biser,

    Thanks for sharing the information. We are now able to assert the GPMC_A11 pin. But facing issue when trying to write the NOR flash upper 128MB. Read and erase are fine. Here are our observation. Note that everything is done in u-boot.

    Read operation:

    We configured the GPMC_A11 pin as GPIO then, we tried to write the sector address 0x18000000 (GPMC_A11 pin configuration is 0x27) and driven high. Then, rebooted the board and while reading the sector it displayed the written data. This will be read by GPMC; GPMC_A11 pin mux configuration is 0x24.

    Erase operation:

    After reading the flash sector; we erased it and then read again. This also succeeded. We confirmed by reading the sector address 0x18000000.

    Write operation:

    We confirmed while trying to write on the flash above 128MB, by probing the GPMC_A11 pin which is getting asserted. But, the content is not actually written. We confirmed it is not writing anywhere else in the NOR flash.

    Please let me know on this.

    -Regards,

    Sankar

  • 0 in reply to Sankar S
    TI__Guru**** 393215 points

    Hi Sankar,

    There has been an update on this from the factory team. The following should be performed in sequence to activate A27 as an address line:

    //FIX for the GPMC 16bit Multiplexed mode for 256MB access using the GPMC_A27 pin 
      
    WR_MEM_32(GPMC_CONFIG1_0,0x00000000); //Reset the Mux Mode
    temp = RD_MEM_32(0x10000000);                   //Access the GPMC Memory to release the GPMC_A27 pin
    WR_MEM_32(GPMC_CONFIG1_0,0x00001210); //16 bit, Multiplexed mode          
     
    The above is based on a GEL file, but the same sequence should be performed during GPMC initialization in Linux. GPMC_A11 should be pinmuxed to mode 4.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 405 points

    Biser, we have already done this in u-boot. After this only we got the GPMC_A11 pin getting asserted.

  • 0 in reply to Sankar S
    Intellectual 405 points

    Biser, we were using the Spansion flash, after updating the patch from Spansion the issue got fixed. Thanks for your support.

  • 0 in reply to Sankar S
    Prodigy 20 points

    Hi Sankar,

    Could you please tel me what you did in u-boot.

    I am also facing the same issue when trying to read a 256MB nand . The read to 128MB is OK but beyond that the read is getting failed.

    Regards,

    Praveen