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Getting camera-data to DM365 DRAM using ISIF

Jasper van Bourgognie37762
Prodigy 60 points


I am trying to get data from a camera(-simulator) into the DRAM, using the ISIF/IPIPEIF on a DM365 processor. For that, I am using MontaVista Linux 5 (from dvsdk 2.10.01.18) and I am _not_ using the V4L VPFE drivers by TI, yet I am controlling the VPSS registers myself by mmapping /dev/mem. I managed to apply a 10 MHz signal to the PCLK pin and get the ISIF to generate VD and HD pulses in return.

Now I am applying a constant signal to the DATA lines (high for even data lines, low for odd ones), a high signal to the WEN pin, the same PCLK of 10 MHz as before and still having the ISIF generate the VD and HD pulses. I set the DRAM address to a physical address that I obtained by using the CMEM module.

In the beginning of my program, after CMEM allocates me my buffer, I wipe it with zeroes. I then set all the registers of the VPSS, including the (to my understanding) CADU and CADL ones. every keystroke I print out the contents of the memory buffer, and all I see are zeroes.

Shortly put, I do not manage to read out the data sent by my camera-simulator in the memory. I have tried several things, especially experimenting with the Write-Enable related registers.

I am out of ideas to fix or debug it, so I was hoping for some input here. If my explanation is unclear or missing important parts, I'm more than happy to share code/output or just clarify things.

Jasper

  • 0
    TI__Mastermind 19985 points

    Jasper,

    There might be some problem in the configuration. i think i understand your usecase and that is DM36x is generating the HD,VD signalling. But have you tested that the HD and VD signals are correctly coming out from DM365? The internal timing generator will work based on the registers like HDW, VDW, PPLN, LPFR that you set in the ISIF.

    So in summary, we need the following to do some analysis:

    1. Configuration registers for ISIF

    2. DDR addresses that you set in CADL and CADU. BTW, these addresses are offset from DDR base address in units of 32 bytes and you should read the correct address when you want to check the output of ISIF.

    3. Check the status of all the signals and verify the interval of HD and VD signals. Also, please check the PCLK and WEN status. Let me know the status and frequency of each of these signals.

     

    Regards,

    Anshuman

  • 0 in reply to Anshuman Saxena
    Prodigy 60 points

    Hi,

    Thank you for your reply. I must say it was of little help, but the reason for that is mysterious to me. The situation is that starting up my setup today, things just seemed to work. No configuration was changed, nothing was recompiled, it just worked. I suppose the reboot of my DM365 device did it. 

    Thanks again.

    Jasper