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Enabling External Memory(DDR3) Non cacheable

Shabrin Firdose

Intellectual 260 points

Hi,

I am working on EVM 6670 multicore, I wanted to remove CACHE_wbL1d(), CACHE_invL1d().
So, I am using MAR register to make external memory(DDR3) non cacheable.
But this change increased machine cycle count by three times.

Can anyone please suggest me which is the best way to remove cache writeback and cache invalid functions?

I need to know what is the difference between cache writeback and disable cache memory(using MAR) for efficient performance?

Regards,
Shabrin

over 11 years ago

0 ToddMullanix over 11 years ago

TI__Guru* 96960 points

Shabrin Firdose said:
I wanted to remove CACHE_wbL1d(), CACHE_invL1d().

I don't know what you mean by this. Do you not want the calls included in your .out file or do you want to remove the need to call these?

Todd

0 Shabrin Firdose over 11 years ago in reply to ToddMullanix

Intellectual 260 points

Hi Todd,

Thanks for your reply, I want to remove the need to call cache writeback and invalid function.

Thanks and Regards,

Shabrin

0 ToddMullanix over 11 years ago in reply to Shabrin Firdose

TI__Guru* 96960 points

Are you sharing the memory in DDR3 with other cores? Where are the calls in question occurring?

Todd

0 Shabrin Firdose over 11 years ago in reply to ToddMullanix

Intellectual 260 points

Yes, I am sharing DDR3 memory with other core.

Thanks and Regards,

Shabrin

0 ToddMullanix over 11 years ago in reply to Shabrin Firdose

TI__Guru* 96960 points

If you use the L2 Cache calls on DDR, they is no need to use the L1 Cache calls.

Todd