HALT and RESET

Avinash Neethi1

Other Parts Discussed in Thread: TMS320C6678

Dear All,

1. We are currently trying to HALT and RESET the C6678 Processor. Is there any ideas for the HALT and RESET concept. In the Tms320C6678 the Standby state is given, but how that can be implemented.

2. Is there any idea for each core reset . In the soft and the hard core reset , the Reset is occurred for the all the eight core. How to perform the single core reset. Assume that the core0 is master then from core0 can I reset all the other 7 core's. Is it possible?

over 11 years ago

0 Bill Taboada over 11 years ago

TI__Mastermind 42545 points

Hi Avinash,

Let me answer your second question. An individual core may be reset using the CORESEL[3:0], the LRESETz and the LRESETNMIEN signals. Details on the timing for these signals can be found in section 7.10.5 of the data manual. To reset an individual core you would drive the proper code on the CORESEL[3:0] pins, set the LRESETz low and then toggle LRESETNMIEN for the proper period of time.

Regards, Bill

0 Avinash Neethi1 over 11 years ago in reply to Bill Taboada

Expert 2125 points

Hi Bill,

The exact issue what we are facing is, We are trying to perform the processor reset and Independent Core reset. We have flashed the Helloworld application in the NOR image-0. After POR the processor loads the application from the NOR Flash.

1. When we are performing the Processor reset the reset is occurred and the application is once again is executed from the NOR Flash.

2. When we are trying for the Core reset, I have made the core 0 to reset and after some time i release the core 0 from the reset. but the application is not running? What can be the issue.

Regards,

Avinash N

0 Raja over 11 years ago in reply to Avinash Neethi1

TI__Guru* 81335 points

Hi Avinash,

Let me answer the first question:

The data manual of C6678 describes how to enable/disable standby mode.

http://www.ti.com/lit/ds/symlink/tms320c6678.pdf

Section: 3.3.11 Power State Control (PWRSTATECTL) Register

Please refer the Hardware design guide to know more about standby mode.

http://www.ti.com/lit/sprabi2

Also refer below e2e link:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/329887/1155498.aspx

Thank you.

0 Bill Taboada over 11 years ago in reply to Avinash Neethi1

TI__Mastermind 42545 points

Hi Avinash,

A core or local reset will not initiate execution from the ROM boot loader. I am assuming that you are using an EMIF boot mode that accesses your NOR flash. A PORz and a RESETFULLz will reset the register values in the EMIF16 and begin to read the code from NOR. The local and core resets will not.

This is described in section 2.2.3 of the Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. B) and in section 5.1.4 of the Hardware Design Guide for KeyStone Devices (Rev. C).

Regards, Bill

0 Avinash Neethi1 over 11 years ago in reply to Bill Taboada

Expert 2125 points

Hi Bill & Rajasekaran,

we can able to perform the FULL reset. What the issue we are facing is, HALT and RESTART.

In our customized board we have flashed separate application .out in each core. Our ultimate aim is to provide the HALT and RESTART. If i set the HALT command the core has to stop the execution and once i set the RESTART command the core has to execute the operation as the continuation of HALT.

Any suggestion or idea for implementation of the above requirement.

Regards,

Avinash N

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HALT and RESET