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Application to download with OMAP-L138_FlashAndBootUtils_2.40 tool

Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Hi,

I created an application with CCSv5.5 and apply this command (into Post-buid steps item) to generate a .bin file :

"${CCS_INSTALL_ROOT}/utils/tiobj2bin/tiobj2bin.bat" "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin" "${CG_TOOL_ROOT}/bin/armofd.exe" "${CG_TOOL_ROOT}/bin/armhex.exe" "${CCS_INSTALL_ROOT}/utils/tiobj2bin/mkhex4bin.exe"

It seems this file is correctly generated.

My purpose is to download this .bin file with OMAP-L138_FlashAndBootUtils_2.40 tool by :

"sfh_OMAPL-L138.exe -flash ubl.bin myAppli.bin"

Downloading works but when I reset card, into terminal I see ubl that excecutes itself but my application doen't work.

See logs :

---------------------------------------------------------------------

Booting TI User Boot Loader
        UBL Version: 1.65
        UBL Flashtype: NAND
Starting NAND Copy...
Valid magicnum, 0x55424CBB, found in block 0x00000006.
   DONE
Jumping to entry point at 0xC1080000.

---------------------------------------------------------------------

1- Is it possible to launch an application like this?

2- How to download my application into RAM or flash without CCS?

Thanks a lot

Sebastien

  • Hi Sebastien,

    What are you trying to do?

    What type of app (ARM or DSP after UBL)  are you want to run ?

    Is there any intended reason to use linux UBL code ?

    Could you please elaborate your requirement?

  • What are you trying to do?

    I have to download and then execute an application developped with CCSv5 but downloading must be done without CCSv5. Is the raison why I thought to FlashAndBootUtils_2.40 tool.

    What type of app (ARM or DSP after UBL)  are you want to run ?

    ARM (built by CCSv5 wih arm compiler)

    Is there any intended reason to use linux UBL code ?

    No, I can use another tool but I don't know how to do this

    Could you please elaborate your requirement?

    My purpose is to download and exectute this application without CCsv5 by using UART terminal or DOS command.

    Have you got specific tools?

  • Hi sebastien,

    Yes, without using CCS, you can flash the ARM app developed by CCS into flash memories such as NAND. That is through the serial flasher utility. We have purposely created  a section in the below TI WIKI and given step by step instruction on "How to flash an ARM app into OMAPl138 LCDK board.using sfh utility."

    http://processors.wiki.ti.com/index.php/OMAPL138_StarterWare_Booting_And_Flashing#How_to_flash_and_boot_the_sample_ARM_starterware_app_on_OMAPL138_LCDK_board

    You can use the starterware Secondary bootloader ( if needed, but not mandatory... As OMAPL138 is an ARM boot device, it can run ARM app directly without bootloader )  itself to boot ARM code instead of linux UBL code.

     

    Regards,

    Shankari.

    -------------------------------------------------------------------------------------------------------

    Please click the Verify Answer button on this post if it answers your question.
    --------------------------------------------------------------------------------------------------------

  • Hi,

    I tried to use StarterWare like specified above but it doesn't work.

    Only bootloader starting but not application.

    My entry point of my application is:

    ENTRY POINT SYMBOL: "_c_int00"  address: c1086158

    Into bootloader I set on bl_main.c:

    unsigned int entryPoint = 0xC1086158;
    unsigned int DspEntryPoint = 0;


    But when bootlader is launching it appears this message "Error: DSP entrypoint (0xC1086158) is not aligned to 1024 bytes. DSP startup aborted."

    Have you got a suggestion?

    Thank you

    Seb

  • Hi Sebatien,

    But when bootlader is launching it appears this message "Error: DSP entrypoint (0xC1086158) is not aligned to 1024 bytes. DSP startup aborted."

    Please align your DSP app to 1KB boundry as like below and please refer the following TI wiki.

    Please modify your DSP linker command file with below changes.

    .text:_c_int00: align=1024 > DDR2


    Please mention your actual memory instead 'DDR' variable.

    http://processors.wiki.ti.com/index.php/OMAPL138_StarterWare_Booting_And_Flashing#Booting_an_ARM.2BDSP_System
  • I don't use DSP; I buit my project with ARM:

    Here my cmd file (DSP_CORE is not defined:

    /****************************************************************************/
    /*  OMAPL138.cmd                                                            */
    /*  Copyright (c) 2010 Texas Instruments Incorporated                       */
    /*  Author: Rafael de Souza                                                 */
    /*                                                                          */
    /*    Description: This file is a sample linker command file that can be    */
    /*                 used for linking programs built with the C compiler and  */
    /*                 running the resulting .out file on an OMAPL138           */
    /*                 device.  Use it as a guideline.  You will want to        */
    /*                 change the memory layout to match your specific          */
    /*                 target system.  You may want to change the allocation    */
    /*                 scheme according to the size of your program.            */
    /*                                                                          */
    /*    Usage:       The map below contains the local memory for each core    */
    /*                 Use the linker option --define=DSP_CORE=n                */
    /*                 Where n defines the core used: DSP (n=1) or ARM (n=0)    */
    /*                                                                          */
    /****************************************************************************/

    MEMORY
    {
    #ifdef DSP_CORE      /* DSP exclusive memory regions */

        DSPL2ROM     o = 0x00700000  l = 0x00100000  /* 1MB L2 DSP local ROM */
        DSPL2RAM     o = 0x00800000  l = 0x00040000  /* 256kB L2 DSP local RAM */
        DSPL1PRAM    o = 0x00E00000  l = 0x00008000  /* 32kB L1 DSP local Program RAM */
        DSPL1DRAM    o = 0x00F00000  l = 0x00008000  /* 32kB L1 DSP local Data RAM */

    #endif

        SHDSPL2ROM   o = 0x11700000  l = 0x00100000  /* 1MB L2 Shared Internal ROM */          
        SHDSPL2RAM   o = 0x11800000  l = 0x00040000  /* 256kB L2 Shared Internal RAM */       
        SHDSPL1PRAM  o = 0x11E00000  l = 0x00008000  /* 32kB L1 Shared Internal Program RAM */
        SHDSPL1DRAM  o = 0x11F00000  l = 0x00008000  /* 32kB L1 Shared Internal Data RAM */       
        EMIFACS0     o = 0x40000000  l = 0x20000000  /* 512MB SDRAM Data (CS0) */
        EMIFACS2     o = 0x60000000  l = 0x02000000  /* 32MB Async Data (CS2) */
        EMIFACS3     o = 0x62000000  l = 0x02000000  /* 32MB Async Data (CS3) */
        EMIFACS4     o = 0x64000000  l = 0x02000000  /* 32MB Async Data (CS4) */
        EMIFACS5     o = 0x66000000  l = 0x02000000  /* 32MB Async Data (CS5) */
        SHRAM        o = 0x80000000  l = 0x00020000  /* 128kB Shared RAM */
        DDR2         o = 0xC1080000  l = 0x20000000  /* 512MB DDR2 Data */

    #ifndef DSP_CORE     /* ARM exclusive memory regions */

        ARMROM       o = 0xFFFD0000  l = 0x00010000  /* 64kB ARM local ROM */
        ARMRAM       o = 0xFFFF0000  l = 0x00002000  /* 8kB ARM local RAM */

    #endif
    }

    SECTIONS
    {
        .text            >  DDR2
        .stack         >  DDR2
        .bss           >  DDR2
        .cio           >  DDR2
        .const         >  DDR2
        .data          >  DDR2
        .switch        >  DDR2
        .sysmem        >  DDR2
        .far           >  DDR2
        .args          >  DDR2
        .ppinfo        >  DDR2
        .ppdata        >  DDR2
        
        /* TI-ABI or COFF sections */
        .pinit         >  DDR2
        .cinit         >  DDR2
        
        /* EABI sections */
        .binit         >  DDR2
        .init_array    >  DDR2
        .neardata      >  DDR2
        .fardata       >  DDR2
        .rodata        >  DDR2
        .c6xabi.exidx  >  DDR2
        .c6xabi.extab  >  DDR2
    }

  • Hi Sebastien,

    Which starterware example are you trying to flash ?

    If you use the TI starterware example then you will see the linker command like this with boundary aligned,

    // ============================================================================
    // Linker Command File for Linking c674 DSP Programs
    //
    // These linker options are for command line linking only. For IDE linking,
    // you should set your linker options in Project Properties.
    //         -c                    Link Using C Conventions
    //        -stack     0x1000        Software Stack Size
    //        -heap    0x1000        Heap Area Size
    // ===========================================================================
    -stack 0x1000
    -heap 0x1000
    
    // ============================================================================
    //                         Specify the System Memory Map
    // ============================================================================
    MEMORY
    {
        L1P:    o = 0x11E00000        l = 0x00008000
        L1D:    o = 0x11F00000        l = 0x00008000
        L2:     o = 0x11800000        l = 0x00040000
        DDR2:   o = 0xC0000000        l = 0x08000000
    }
    
    // ============================================================================
    //                 Specify the Sections Allocation into Memory
    // ============================================================================
    SECTIONS
    {
        .cinit        >        DDR2               // Initialization Tables
        .pinit        >        DDR2               // Constructor Tables
        .init_array   >        DDR2               // 
        .binit        >        DDR2               // Boot Tables
        .const        >        DDR2               // Constant Data
        .switch       >        DDR2               // Jump Tables
        .text         >        DDR2               // Executable Code
        .text:_c_int00: align=1024 > DDR2         // Entrypoint
        
        GROUP (NEARDP_DATA)                       // group near data
        {
           .neardata
           .rodata
           .bss                                   // note: removed fill = 0
        }             >        DDR2
        .far: fill = 0x0, load > DDR2             // Far Global & Static Variables
        .fardata      >        DDR2               // Far RW Data
        .stack        >        DDR2               // Software System Stack
        .sysmem       >        DDR2               // Dynamic Memory Allocation Area
        
        .cio          >        DDR2               // C I/O Buffer
        .vecs         >        DDR2               // Interrupt Vectors
    }

  • I added ".text:_c_int00: align=1024 > DDR2 // Entrypoint" but It doesn't change

    "ENTRY POINT SYMBOL: "_c_int00"  address": c1086158 into map file created after building.

    And so I don't understand why bootloader want to run DSP application whereas I use ARM application.

  • Hi Sebastien,

    And so I don't understand why bootloader want to run DSP application whereas I use ARM application.

    Where this information had mentioned that "bootloader want to run DSP app" ?

    If you want to flash the starterware examples on flash then we need starterware's bootloader to call ARM or DSP app.

    The Shankari mentioned wiki has mentioned that we can flash the ARM app, DSP app, and ARM+DSP app.

    You can flash ARM app alone or DSP alone or also ARM+DSP apps but only with starterware bootloaders since starterware bootloader code has the information where we need to read the code (SPI/NAND)

    Please read the TI wiki line by line and also flash the starterware GPIO examples on TI EVM boards.

    Please write back if you have further queries.

    http://processors.wiki.ti.com/index.php/OMAPL138_StarterWare_Booting_And_Flashing

  • It's on the hyperterminal I see bootloader wants to run DSP application :

    See my logs in red color :

    ---------------------------------------------------------------------------------------------------------------

    StarterWare OMAPL138 Boot Loader
    Jumping to StarterWare Application...

    Running DSP Application...
    Error: DSP entrypoint (0xC1086158) is not aligned to 1024 bytes. DSP startup aborted.

    ---------------------------------------------------------------------------------------------------------------

  • Hi,

    Disable "DSPentry point" then try and don't give any address to DSP entry point.

  • Ok.

    May be the problem is in the generation to MyAppli.bin from MyAppli.out.

    I converted it with "out2rprc.exe [application].out [application].bin"

    And when I open this .bin file I see data starting to RPRC...

    This command adds informations into .bin file!

    How can I do to be sure my application is wellness installed to DDR2 and it is not corrupted?

    Thanks

  • Hi Sebastien,

    Yes, the out2rprc will add some header information to the bin file while converting *.out to *.bin but that need not be confused here.

    Your error seems to be DSP entry point address is not aligned to 1024.

    Try some standard working examples first without any modifications. All the starterware working examples has its app entry point aligned to 1024

     

    Regards,

    Shankari

  • Hi,

    ok thank you.

    I found the issue. It was due to bad DDR2 settings.

  • Hi Sebastien,

    Sounds good.

    Thanks for your update.

  • Hi Sebastien,

    Thanks for the update.

    Would you please share the information on how did you fix the problem; So that it will be useful for other customers who come across the same problem.

    Describing like how was the DDR2 settings before and now?!!.

     

    Regards,

    Shankari

  • Hi,

    I changed settings corresponding to my DDR2 in DDRInit(void) function into bl_platform.c (/bootloader/src/armv5/omapl138 folder).

    I use platform lcdkOMAPL138.

    I use DDR2 K4T1G164QF-BCF8.

    ------------------------------------------------------------------------------------------------

    #elif  (defined lcdkOMAPL138)
        // Settings depending on DDR2
        tmp_SDCR =     (0x0               << 25)  |  // MSDRAMEN
                       (0x1               << 20);    // DDR2EN


        HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) =
                       tmp_SDCR                    |  // Settings that change depending on DDR2 or MDDR
                       (HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) & 0xF0000000) |  // Reserved
                       (0x0               << 27)   |  // DDR2TERM1
                       (0x0               << 26)   |  // IBANK_POS
                       (0x0               << 24)   |  // DDRDRIVE1
                       (0x0               << 23)   |  // BOOTUNLOCK
                       (0x0               << 22)   |  // DDR2DDQS
                       (0x0               << 21)   |  // DDR2TERM0
                       (0x0               << 19)   |  // DDRDLL_DIS
                       (0x0               << 18)   |  // DDRDRIVE0
                       (0x1               << 17)   |  // DDREN
                       (0x1               << 16)   |  // SDRAMEN
                       (/*0x1*/0x0               << 15)   |  // TIMUNLOCK
                       (0x1               << 14)   |  // NM
                       (0x0               << 12)   |  // Reserved
                       (/*0x4*/0x5               << 9)    |  // CL
                       (0x0               << 7)    |  // Reserved
                       (/*0x3*/0x2               << 4)    |  // IBANK
                       (0x0               << 3)    |  // Reserved
                       (0x2               << 0);      // PAGESIZE

        HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR2)   = 0x00000000; // IBANK_POS set to 0 so this register does not apply

        
        /* Let float -> integer truncate handle minus 1; Safer to round up for timings */
        HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDTIMR1) =
                            (((unsigned int) (/*127.5*/150 * freq / 1000))  << 25)         |  // tRFC
                            (((unsigned int) (/*13.13*/30 * freq / 1000))  << 22)         |  // tRP
                            (((unsigned int) (/*13.13*/30 * freq / 1000))  << 19)         |  // tRCD
                            (((unsigned int) ( /*15.0*/30 * freq / 1000))  << 16)         |  // tWR
                            (((unsigned int) ( /*45.0*/1000 * freq / 1000))  << 11)         |  // tRAS
                            (((unsigned int) (/*58.13*/100 * freq / 1000))  << 6)          |  // tRC
                            (((unsigned int) (  /*7.5*/20 * freq / 1000))  << 3)          |  // tRRD
                            (HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDTIMR1) & 0x4) |  // Reserved
                            ((/*2*/15 - 1)                                 << 0);     // tWTR

        HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDTIMR2) =
                            (HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDTIMR2) & 0x80000000) |  // Reserved
                            (((unsigned int) ((70000 / 7800) - 1))   << 27)   |  // tRASMAX (original 3400)
                            ((/*0x3*/0x4-1)                                 << 25)   |  // tXP (Should be 6-1 per MT46H64M16LFBF-6 datasheet, but field only goes up to 0b11)
                            (0x0                                     << 23)   |  // tODT (Not supported)
                            (((unsigned int) (/*137.5*/300 * freq / 1000))  << 16)   |  // tXSNR (tXSR for mDDR)
                            ((/*200*/250-1)                                   << 8)    |  // tXSRD (tXSR for mDDR)
                            ((/*2*/15 - 1)                                 << 5)    |  // tRTP
                            ((/*3*/10 - 1)                                 << 0);      // tCKE
     
        /* CLEAR TIMINGUNLOCK */
        HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) &= ~DDR2_MDDR_SDCR_BOOTUNLOCK;    
        
        /* SET the refreshing rate */
        HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR) = DDR2_SDRCR;    

        // Let float -> integer truncate handle RR round-down; Safer to round down for refresh rate
        HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR)   =
                          (/*0x1*/0x0                                  << 31)  |  // LPMODEN (Required for LPSC SyncReset/Enable)
                          (/*0x1*/0x0                                  << 30)  |  // MCLKSTOPEN (Required for LPSC SyncReset/Enable)
                          (0x0                                  << 24)  |  // Reserved
                          (0x0                                  << 23)  |  // SR_PD
                          (0x0                                  << 16)  |  // Reserved
                          (((unsigned int) (/*7.8*/3 * freq))          << 0);     // RR  (original 7.8125)

    #endif

    ------------------------------------------------------------------------------------------------