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Errata 2.1.2 Some PLLs Only Support Even M2 Post Dividers

Stephen Turner
Genius 3476 points

Hi


I'd like to know what happens if you use an odd M2 PLL post divider.  The errata says don't do it, without explaining why or what happens if you do.  We are currently using an odd divider for our VIDEO0 PLL and don't see any issues.

thanks

Steve

  • 0
    TI__Guru**** 170625 points

    Steve,

    Odd value of M2 will result in Non-50% duty cycle. Please note that M2 is a post divider and is not part of the loop. Hence non 50% duty cycle on this should not impact the loop performance. The PLL should not unlock due to this.

    The drawback of using odd M2: Generally, any half cycle paths on this clock, timing will be impacted. Pulse width requirements for clock will also get impacted.

    Regards,
    Pavel

  • 0
    Mastermind 8040 points

    To add to what Pavel said, just in case it's not already obvious:  to ensure minimum low and high times are satisfied with an asymmetric duty cycle, the maximum allowable speed of the affected clock (and any derived clock with odd divisor) would be reduced compared to what the datasheet specifies.  This is tricky since the amount of asymmetry isn't characterized (and might perhaps be process/voltage/temperature-dependent).

    Stephen Turner said:
    and don't see any issues.

    I suspect one can typically run slightly outside the specs without obvious issues.  Indeed there are whole communities dedicated to empirically discovering how far outside the specs one can run hardware.  I do get the impression long-term reliability may be adversely affected though ;-)