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DDR3A, DDR3B partition for 66AK2H14

Ellen Kou
Intellectual 1110 points

Hello,

A customer is asking if we have a set or recommended architecture/plan on how to partition the DDR3A and DDR3B memory across the ARM and DSP cores for the 66AK2Hxx. Do we have any guidelines or recommnedations for this?

 

Thanks,

Ellen

  • 0
    TI__Expert 6815 points

    Hi Ellen,

    Let me answer from a generic usage perspective that covers non-core masters as well. My hope is that this serves as a guideline for customers to make decisions.

    The EMIF for DDR3A being attached directly to MSMC has a number of advantages for both ARM and DSP cores:

    1) It is closer (lower read latency) than DDR3B for all of them, offering definite performance advantages.

    2) DDR3A supports a larger physical address space of 8GB compared to 2GB for DDR3B. This allows users to alllocate larger private and shared spaces.

    3) For ARM cores, there is the added benefit of IO/DMA coherence when using DDR3A.

    4) The non-core masters on the device can be configured to access upto 2GB in any part of the 8GB DDR3A space, as opposed to a fixed 512MB on DDR3B.

    From a superset platform perspective, DDR3B exists for two reasons:

    1)  Provide support for wireless co-processors that use small and random accesses that are naturally less efficient for DDR3 EMIFs. This inefficient bandwidth use can be offloaded from DDR3A when using DDR3B.

    2) The data being stored there was going to be used by other co-processors instead of the cores which are further away from DDR3B and closer to DDR3A.

    For device variants that do not have wireless co-processors, it is probably best to consider populating and using DDR3B only in cases which justify specific use of that memory...like intermediate storage where the data will not be created or consumed by the cores and will offload those memory accesses from DDR3A.

  • 0 in reply to Aditya
    Intellectual 380 points
    This was a good information about the DDR3A and B.

    We have an application where we have constant data flow coming from sensors (@ about 8MBytes / sec) through EMIF interface. The idea would be to transfer this by EDMA to DDR3B (from EMIF -> 3B) and then to copy this to 3A in batches for data calculation ("ping pong buffer"). EMIF data transfer efficiency has been verified already on our existing DaVinci custom card but due to heavy algorithm we have to move to K2H. I'm doing the DSP card design at the moment and would like to know wheter to include the DDR3B at all.

    All suggestions are more than welcome!
  • 0 in reply to Zeb
    Intellectual 380 points
    Referring to Aditya's reply, it is a bit strange that 3B has higher latency. If you read the document sprabk5b (throughput performance guide for KeyStone II devices), page 18 & 19 (tables 14 & 15), throughput in corepac transfer shows same data for A and B using EDMA. On the other hand, tables 11 &12 show that B is slightly less efficient but in my opinion this is nothing serious.

    Can one use the DDR3B for program and data? The same doc states "The TeraNet also provides a 64-bit DDR3A and 64-bit DDR3B interface to support access to external memories that can be used for either data or program memory" - I guess this tells it that it is possibe?