Hello,
A customer is asking if we have a set or recommended architecture/plan on how to partition the DDR3A and DDR3B memory across the ARM and DSP cores for the 66AK2Hxx. Do we have any guidelines or recommnedations for this?
Thanks,
Ellen
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Hello,
A customer is asking if we have a set or recommended architecture/plan on how to partition the DDR3A and DDR3B memory across the ARM and DSP cores for the 66AK2Hxx. Do we have any guidelines or recommnedations for this?
Thanks,
Ellen
Hi Ellen,
Let me answer from a generic usage perspective that covers non-core masters as well. My hope is that this serves as a guideline for customers to make decisions.
The EMIF for DDR3A being attached directly to MSMC has a number of advantages for both ARM and DSP cores:
1) It is closer (lower read latency) than DDR3B for all of them, offering definite performance advantages.
2) DDR3A supports a larger physical address space of 8GB compared to 2GB for DDR3B. This allows users to alllocate larger private and shared spaces.
3) For ARM cores, there is the added benefit of IO/DMA coherence when using DDR3A.
4) The non-core masters on the device can be configured to access upto 2GB in any part of the 8GB DDR3A space, as opposed to a fixed 512MB on DDR3B.
From a superset platform perspective, DDR3B exists for two reasons:
1) Provide support for wireless co-processors that use small and random accesses that are naturally less efficient for DDR3 EMIFs. This inefficient bandwidth use can be offloaded from DDR3A when using DDR3B.
2) The data being stored there was going to be used by other co-processors instead of the cores which are further away from DDR3B and closer to DDR3A.
For device variants that do not have wireless co-processors, it is probably best to consider populating and using DDR3B only in cases which justify specific use of that memory...like intermediate storage where the data will not be created or consumed by the cores and will offload those memory accesses from DDR3A.