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TMS320C6474 - EVM & DDR2

Bubsy
Intellectual 300 points
Other Parts Discussed in Thread: TMS320C6474

Hello,

I'm requesting your help concerning the 2 items linked to the DSP C64x+ and EVM :

1  .  Could you confirm me that the DDR2 used and connected is 256MB (2*128MB) of 667MHz DDR2 per DSP ? Because in the TI documentation (see "http://focus.ti.com/docs/toolsw/folders/print/tmdxevm6474.html") it is written "256MB of 667MHz DDR2 per C6474 DSP" and in the Digital Spectrum documentation (see "http://support.spectrumdigital.com/boards/evmc6474/revb/files/EVMC6474_TechRef_RevB.pdf"), we can see on page 10 §1.2 : 128 MB of DDR2 memory for each processor ?

2  .  Concerning the clock speed, could you confirm me that in my configuration (TMS320C6474 - EVM), for example if the DSP and L1 speed is 1GHz, the L2 speed will be 500MHz ? For TI's DSP, could I conclude that L2 speed is 50% lower that DSP & L1 ?

D'avance merci

Bubsy

 

  • 0
    TI__Guru* 84110 points

    Bubsy said:
    Could you confirm me that the DDR2 used and connected is 256MB



    In the Spectrum Digital Tech Ref you reference, on page 80 is the schematic for the DDR2s. The schematic calls out part number MT47H64M16HR-3:E which Micron says is a 64Mx16bit memory or 128MBytes per chip. This would mean there are 256MBytes per C6474. My vote is for 256MB, but if you want to know what you will get if you order one, contact SD sales and ask them. They will be interested in correcting the discrepancy, whichever way is correct.

    When I find discrepancies, I prefer to find out the real answer explicitly rather than asking. There could have been board revs or schematic changes. So assuming you have a board, open up CCS, connect to one of the cores, write unique values at the start and end of DDR space as if there is 256MB and see if the locations stay unique.

    Bubsy said:
    Concerning the clock speed, could you confirm me that in my configuration (TMS320C6474 - EVM), for example if the DSP and L1 speed is 1GHz, the L2 speed will be 500MHz ? For TI's DSP, could I conclude that L2 speed is 50% lower that DSP & L1 ?


    These are misleading questions, in my opinion. L1P and L1D are faster memories and are located physically closer to the C64x+ core to allow 0 wait state access. L2 memory is substantially larger and provides an interface to the external memories plus additional cache space. The banking structure, bus widths, buffers, and cache features provide non-linear relationships between "L2 speed" and "clock speed" and between "L2 speed" and "L1x speed".

    The datasheet states that the DSPCLK/2 is what is supplied to the L2, so yes, it is clocked at a lower rate. But no, you should not conclude that L2 is 50% slower than L1x.

    The memory architecture and memory performance are not nearly that easy to explain or to characterize on paper. There are tables in the Megamodule Ref Guide that show L1P cache read misses that go to L2 SRAM or L2 Cache can have identical performance as L1P hits, or maybe average at 20% slower for a "normal" mix of simple program code. Data performance can be dependent on the algorithm and the data allocation/alignment.

    Benchmark what you want to run. Use a Device Simulator that comprehends L1 and L2 SRAM and cache effects; the simulator has more memory/cache analysis tools available. And more accurately, run on silicon and use the Time Stamp Counter to calculate timing. Just make sure you have everything turned on and enabled to get the most realistic results.