What is the GPMC_FCLK frequency during boot-time?
Tech Ref 24.4.7.3 says GPMC_CLK is 48Mhz however, that is not even driven during booting because the GPMC uses asynchronous protocol to access XIP flash.
Section 24.4.4.2 says L3.ICLK is 96Mhz. I think this is what drives GPMC_FCLK. Is this correct?
If so, then the divide-by setting between GPMC_FLCK and GPMC_CLK must be set to 2.
Is it correct that in general many of the clocks are multiples of 24Mhz?
Is this left over from a previous device spec?
It seems like for the Am3505 they would be multiples of 26 Mhz since that is the input clock.