McASP Transmit in OMAPL138

521177 103
R McASP0DSP_REVID 0x0000000B 0x44300A02
R McASP0DSP_PFUNC 0x0000000B 0x00000000
R McASP0DSP_PDIR 0x0000000B 0x1C000800
R McASP0DSP_PDOUT 0x0000000B 0x00000000
R McASP0DSP_PDIN 0x0000000B 0xF200F7FB
R McASP0DSP_PDSET 0x0000000B 0xE600F7FB
R McASP0DSP_PDCLR 0x0000000B 0x00000000
R McASP0DSP_GBLCTL 0x0000000B 0x00001F1F
R McASP0DSP_AMUTE 0x0000000B 0x00000000
R McASP0DSP_DLBCTL 0x0000000B 0x00000000
R McASP0DSP_DITCTL 0x0000000B 0x00000000
R McASP0DSP_RGBLCTL 0x0000000B 0x00001F1F
R McASP0DSP_RMASK 0x0000000B 0xFFFFFFFF
R McASP0DSP_RFMT 0x0000000B 0x000180F8
R McASP0DSP_AFSRCTL 0x0000000B 0x00000113
R McASP0DSP_ACLKRCTL 0x0000000B 0x000000A0
R McASP0DSP_AHCLKRCTL 0x0000000B 0x00008000
R McASP0DSP_RTDM 0x0000000B 0x00000003
R McASP0DSP_RINTCTL 0x0000000B 0x00000000
R McASP0DSP_RSTAT 0x0000000B 0x0000017D
R McASP0DSP_RSLOT 0x0000000B 0x00000000
R McASP0DSP_RCLKCHK 0x0000000B 0x00000000
R McASP0DSP_REVTCTL 0x0000000B 0x00000000
R McASP0DSP_XGBLCTL 0x0000000B 0x00001F1F
R McASP0DSP_XMASK 0x0000000B 0xFFFFFFFF
R McASP0DSP_XFMT 0x0000000B 0x000080F8
R McASP0DSP_AFSXCTL 0x0000000B 0x00000113
R McASP0DSP_ACLKXCTL 0x0000000B 0x00000027
R McASP0DSP_AHCLKXCTL 0x0000000B 0x00008000
R McASP0DSP_XTDM 0x0000000B 0x00000003
R McASP0DSP_XINTCTL 0x0000000B 0x000000BF
R McASP0DSP_XSTAT 0x0000000B 0x00000179
R McASP0DSP_XSLOT 0x0000000B 0x00000001
R McASP0DSP_XCLKCHK 0x0000000B 0x32322F02
R McASP0DSP_XEVTCTL 0x0000000B 0x00000000
R McASP0DSP_DITCSRA0 0x0000000B 0x00000000
R McASP0DSP_DITCSRA1 0x0000000B 0x00000000
R McASP0DSP_DITCSRA2 0x0000000B 0x00000000
R McASP0DSP_DITCSRA3 0x0000000B 0x00000000
R McASP0DSP_DITCSRA4 0x0000000B 0x00000000
R McASP0DSP_DITCSRA5 0x0000000B 0x00000000
R McASP0DSP_DITCSRB0 0x0000000B 0x00000000
R McASP0DSP_DITCSRB1 0x0000000B 0x00000000
R McASP0DSP_DITCSRB2 0x0000000B 0x00000000
R McASP0DSP_DITCSRB3 0x0000000B 0x00000000
R McASP0DSP_DITCSRB4 0x0000000B 0x00000000
R McASP0DSP_DITCSRB5 0x0000000B 0x00000000
R McASP0DSP_DITUDRA0 0x0000000B 0x00000000
R McASP0DSP_DITUDRA1 0x0000000B 0x00000000
R McASP0DSP_DITUDRA2 0x0000000B 0x00000000
R McASP0DSP_DITUDRA3 0x0000000B 0x00000000
R McASP0DSP_DITUDRA4 0x0000000B 0x00000000
R McASP0DSP_DITUDRA5 0x0000000B 0x00000000
R McASP0DSP_DITUDRB0 0x0000000B 0x00000000
R McASP0DSP_DITUDRB1 0x0000000B 0x00000000
R McASP0DSP_DITUDRB2 0x0000000B 0x00000000
R McASP0DSP_DITUDRB3 0x0000000B 0x00000000
R McASP0DSP_DITUDRB4 0x0000000B 0x00000000
R McASP0DSP_DITUDRB5 0x0000000B 0x00000000
R McASP0DSP_SRCTL0 0x0000000B 0x00000000
R McASP0DSP_SRCTL1 0x0000000B 0x00000000
R McASP0DSP_SRCTL2 0x0000000B 0x00000000
R McASP0DSP_SRCTL3 0x0000000B 0x00000000
R McASP0DSP_SRCTL4 0x0000000B 0x00000000
R McASP0DSP_SRCTL5 0x0000000B 0x00000000
R McASP0DSP_SRCTL6 0x0000000B 0x00000000
R McASP0DSP_SRCTL7 0x0000000B 0x00000000
R McASP0DSP_SRCTL8 0x0000000B 0x00000000
R McASP0DSP_SRCTL9 0x0000000B 0x00000000
R McASP0DSP_SRCTL10 0x0000000B 0x00000000
R McASP0DSP_SRCTL11 0x0000000B 0x00000011
R McASP0DSP_SRCTL12 0x0000000B 0x00000022
R McASP0DSP_SRCTL13 0x0000000B 0x00000000
R McASP0DSP_SRCTL14 0x0000000B 0x00000000
R McASP0DSP_SRCTL15 0x0000000B 0x00000000
R McASP0DSP_XBUF0 0x0000000B 0x00000000
R McASP0DSP_XBUF1 0x0000000B 0x00000000
R McASP0DSP_XBUF2 0x0000000B 0x00000000
R McASP0DSP_XBUF3 0x0000000B 0x00000000
R McASP0DSP_XBUF4 0x0000000B 0x00000000
R McASP0DSP_XBUF5 0x0000000B 0x00000000
R McASP0DSP_XBUF6 0x0000000B 0x00000000
R McASP0DSP_XBUF7 0x0000000B 0x00000000
R McASP0DSP_XBUF8 0x0000000B 0x00000000
R McASP0DSP_XBUF9 0x0000000B 0x00000000
R McASP0DSP_XBUF10 0x0000000B 0x00000000
R McASP0DSP_XBUF11 0x0000000B 0x00000000
R McASP0DSP_XBUF12 0x0000000B 0xFFFFFFFF
R McASP0DSP_XBUF13 0x0000000B 0x00000000
R McASP0DSP_XBUF14 0x0000000B 0x00000000
R McASP0DSP_XBUF15 0x0000000B 0x00000000
R McASP0DSP_RBUF0 0x0000000B 0x00000000
R McASP0DSP_RBUF1 0x0000000B 0x00000000
R McASP0DSP_RBUF2 0x0000000B 0x00000000
R McASP0DSP_RBUF3 0x0000000B 0x00000000
R McASP0DSP_RBUF4 0x0000000B 0x00000000
R McASP0DSP_RBUF5 0x0000000B 0x00000000
R McASP0DSP_RBUF6 0x0000000B 0x00000000
R McASP0DSP_RBUF7 0x0000000B 0x00000000
R McASP0DSP_RBUF8 0x0000000B 0x00000000
R McASP0DSP_RBUF9 0x0000000B 0x00000000
R McASP0DSP_RBUF10 0x0000000B 0x00000000
R McASP0DSP_RBUF11 0x0000000B 0x00000000
R McASP0DSP_RBUF12 0x0000000B 0xFFFFFFFF
R McASP0DSP_RBUF13 0x0000000B 0x00000000
R McASP0DSP_RBUF14 0x0000000B 0x00000000
R McASP0DSP_RBUF15 0x0000000B 0x00000000
R McASPFIFO0DSP_REVID 0x0000000B 0x44311100
R McASPFIFO0DSP_WFIFOCTL 0x0000000B 0x00001004
R McASPFIFO0DSP_WFIFOSTS 0x0000000B 0x00000000
R McASPFIFO0DSP_RFIFOCTL 0x0000000B 0x00001004
R McASPFIFO0DSP_RFIFOSTS 0x0000000B 0x00000000

521177 103
R McASP0DSP_REVID 0x0000000B 0x44300A02
R McASP0DSP_PFUNC 0x0000000B 0x00000000
R McASP0DSP_PDIR 0x0000000B 0x1C000800
R McASP0DSP_PDOUT 0x0000000B 0x00000000
R McASP0DSP_PDIN 0x0000000B 0xE600F7FB
R McASP0DSP_PDSET 0x0000000B 0xE600F7FB
R McASP0DSP_PDCLR 0x0000000B 0x00000000
R McASP0DSP_GBLCTL 0x0000000B 0x00001F1F
R McASP0DSP_AMUTE 0x0000000B 0x00000000
R McASP0DSP_DLBCTL 0x0000000B 0x00000005
R McASP0DSP_DITCTL 0x0000000B 0x00000000
R McASP0DSP_RGBLCTL 0x0000000B 0x00001F1F
R McASP0DSP_RMASK 0x0000000B 0xFFFFFFFF
R McASP0DSP_RFMT 0x0000000B 0x000180F8
R McASP0DSP_AFSRCTL 0x0000000B 0x00000113
R McASP0DSP_ACLKRCTL 0x0000000B 0x000000A0
R McASP0DSP_AHCLKRCTL 0x0000000B 0x00008000
R McASP0DSP_RTDM 0x0000000B 0x00000003
R McASP0DSP_RINTCTL 0x0000000B 0x00000000
R McASP0DSP_RSTAT 0x0000000B 0x00000175
R McASP0DSP_RSLOT 0x0000000B 0x00000000
R McASP0DSP_RCLKCHK 0x0000000B 0x00000000
R McASP0DSP_REVTCTL 0x0000000B 0x00000000
R McASP0DSP_XGBLCTL 0x0000000B 0x00001F1F
R McASP0DSP_XMASK 0x0000000B 0xFFFFFFFF
R McASP0DSP_XFMT 0x0000000B 0x000080F8
R McASP0DSP_AFSXCTL 0x0000000B 0x00000113
R McASP0DSP_ACLKXCTL 0x0000000B 0x00000027
R McASP0DSP_AHCLKXCTL 0x0000000B 0x00008000
R McASP0DSP_XTDM 0x0000000B 0x00000003
R McASP0DSP_XINTCTL 0x0000000B 0x000000BF
R McASP0DSP_XSTAT 0x0000000B 0x00000179
R McASP0DSP_XSLOT 0x0000000B 0x00000001
R McASP0DSP_XCLKCHK 0x0000000B 0x31322F02
R McASP0DSP_XEVTCTL 0x0000000B 0x00000000
R McASP0DSP_DITCSRA0 0x0000000B 0x00000000
R McASP0DSP_DITCSRA1 0x0000000B 0x00000000
R McASP0DSP_DITCSRA2 0x0000000B 0x00000000
R McASP0DSP_DITCSRA3 0x0000000B 0x00000000
R McASP0DSP_DITCSRA4 0x0000000B 0x00000000
R McASP0DSP_DITCSRA5 0x0000000B 0x00000000
R McASP0DSP_DITCSRB0 0x0000000B 0x00000000
R McASP0DSP_DITCSRB1 0x0000000B 0x00000000
R McASP0DSP_DITCSRB2 0x0000000B 0x00000000
R McASP0DSP_DITCSRB3 0x0000000B 0x00000000
R McASP0DSP_DITCSRB4 0x0000000B 0x00000000
R McASP0DSP_DITCSRB5 0x0000000B 0x00000000
R McASP0DSP_DITUDRA0 0x0000000B 0x00000000
R McASP0DSP_DITUDRA1 0x0000000B 0x00000000
R McASP0DSP_DITUDRA2 0x0000000B 0x00000000
R McASP0DSP_DITUDRA3 0x0000000B 0x00000000
R McASP0DSP_DITUDRA4 0x0000000B 0x00000000
R McASP0DSP_DITUDRA5 0x0000000B 0x00000000
R McASP0DSP_DITUDRB0 0x0000000B 0x00000000
R McASP0DSP_DITUDRB1 0x0000000B 0x00000000
R McASP0DSP_DITUDRB2 0x0000000B 0x00000000
R McASP0DSP_DITUDRB3 0x0000000B 0x00000000
R McASP0DSP_DITUDRB4 0x0000000B 0x00000000
R McASP0DSP_DITUDRB5 0x0000000B 0x00000000
R McASP0DSP_SRCTL0 0x0000000B 0x00000000
R McASP0DSP_SRCTL1 0x0000000B 0x00000000
R McASP0DSP_SRCTL2 0x0000000B 0x00000000
R McASP0DSP_SRCTL3 0x0000000B 0x00000000
R McASP0DSP_SRCTL4 0x0000000B 0x00000000
R McASP0DSP_SRCTL5 0x0000000B 0x00000000
R McASP0DSP_SRCTL6 0x0000000B 0x00000000
R McASP0DSP_SRCTL7 0x0000000B 0x00000000
R McASP0DSP_SRCTL8 0x0000000B 0x00000000
R McASP0DSP_SRCTL9 0x0000000B 0x00000000
R McASP0DSP_SRCTL10 0x0000000B 0x00000000
R McASP0DSP_SRCTL11 0x0000000B 0x00000011
R McASP0DSP_SRCTL12 0x0000000B 0x00000022
R McASP0DSP_SRCTL13 0x0000000B 0x00000000
R McASP0DSP_SRCTL14 0x0000000B 0x00000000
R McASP0DSP_SRCTL15 0x0000000B 0x00000000
R McASP0DSP_XBUF0 0x0000000B 0x00000000
R McASP0DSP_XBUF1 0x0000000B 0x00000000
R McASP0DSP_XBUF2 0x0000000B 0x00000000
R McASP0DSP_XBUF3 0x0000000B 0x00000000
R McASP0DSP_XBUF4 0x0000000B 0x00000000
R McASP0DSP_XBUF5 0x0000000B 0x00000000
R McASP0DSP_XBUF6 0x0000000B 0x00000000
R McASP0DSP_XBUF7 0x0000000B 0x00000000
R McASP0DSP_XBUF8 0x0000000B 0x00000000
R McASP0DSP_XBUF9 0x0000000B 0x00000000
R McASP0DSP_XBUF10 0x0000000B 0x00000000
R McASP0DSP_XBUF11 0x0000000B 0xFFFFFFFF
R McASP0DSP_XBUF12 0x0000000B 0xFFFFFFFF
R McASP0DSP_XBUF13 0x0000000B 0x00000000
R McASP0DSP_XBUF14 0x0000000B 0x00000000
R McASP0DSP_XBUF15 0x0000000B 0x00000000
R McASP0DSP_RBUF0 0x0000000B 0x00000000
R McASP0DSP_RBUF1 0x0000000B 0x00000000
R McASP0DSP_RBUF2 0x0000000B 0x00000000
R McASP0DSP_RBUF3 0x0000000B 0x00000000
R McASP0DSP_RBUF4 0x0000000B 0x00000000
R McASP0DSP_RBUF5 0x0000000B 0x00000000
R McASP0DSP_RBUF6 0x0000000B 0x00000000
R McASP0DSP_RBUF7 0x0000000B 0x00000000
R McASP0DSP_RBUF8 0x0000000B 0x00000000
R McASP0DSP_RBUF9 0x0000000B 0x00000000
R McASP0DSP_RBUF10 0x0000000B 0x00000000
R McASP0DSP_RBUF11 0x0000000B 0xFFFFFFFF
R McASP0DSP_RBUF12 0x0000000B 0xFFFFFFFF
R McASP0DSP_RBUF13 0x0000000B 0x00000000
R McASP0DSP_RBUF14 0x0000000B 0x00000000
R McASP0DSP_RBUF15 0x0000000B 0x00000000
R McASPFIFO0DSP_REVID 0x0000000B 0x44311100
R McASPFIFO0DSP_WFIFOCTL 0x0000000B 0x00001004
R McASPFIFO0DSP_WFIFOSTS 0x0000000B 0x00000000
R McASPFIFO0DSP_RFIFOCTL 0x0000000B 0x00001004
R McASPFIFO0DSP_RFIFOSTS 0x0000000B 0x00000000

Trouble Reading Memory Block at 0x1e25028 on Page 0 of Length 0x4:
(Error -1202 @ 0x1E25028)
Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further.
(Emulation package 5.1.73.0

//Project  Name: quickStartOMAPL1x McASP Chip Support Library Example
//Texas Instruments Device Platform: Logic Product Development OMAP-L138 Experimentor Kit
//Copywrite (c) 2011 Texas Instruments Incroporated

/*===============================================================*/
/****************************LICENSE *****************************/
/*===============================================================*/
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*/


//*==================================================*/
//********************Includes *********************/
//*==================================================*/
//*Non-DSP/BIOS5 Header Files*/
#include <ti/pspiom/cslr/tistdtypes.h>	
#include "mcasp.h"



//==================================================/
//***************Function Prototypes ***************/
//==================================================/
void McASPInit(void);
void McASPStart(void);
void McASPStart(void);



//==================================================/
//*********Global Variable Instantiations **********/
//==================================================/

//McASP0 Control Registers
CSL_McaspRegsOvly mcaspRegs = (CSL_McaspRegsOvly) CSL_MCASP_0_CTRL_REGS;	//OMAP-L138 McASP Configuration Register Pointer Instance

//McASP AFIFO Control Registers
CSL_AfifoRegsOvly afifoRegs = (CSL_AfifoRegsOvly) CSL_MCASP_0_FIFO_REGS;

//McASP DMA Port Registers
CSL_AdataRegsOvly adataRegs = (CSL_AdataRegsOvly) CSL_MCASP_0_DATA_REGS;


//==================================================/
//**********Functions ******************************/
//* This function is used to initialize the McASP*/
//==================================================/

//Notes: On Logic 1013527 Baseboard Hardware Mapping
//  AIC BCLK: connected to M_ACLKX/GPIO[14]
//  AIC WCLK: connected to M_AFSX/GPIO[12]
//  AIC DIN:  connected to M_AXR11 (OMAP-L138 Tx)
//  AIC DOUT  connected to M_AXR12 (OMAP-L138 Rx)
//  AIC MCLK  connected to M_AHCLKX (connected to 24.576MHz XTAL)

//OMAP-L138 Clocking Configuration
//AHCLKX -> External
//ACLKX  -> Internal / -> AHCLK/8
//AFSX   -> Interal -> Auto Generated by FS Gen.


void McASPInit(void)
{
	
/*This function will be called by Main to Initialize the McASP */
/* Although this configuration can be done completely by hand, we chose to use the 
 * OMAP-L138 Chip Support Library (CSL) because those functions presumably already
 *  work and are tested*/

	
//Initialize the McASP Registers for use on the LogicPD OMAP-L138 SOM/Baseboard.

/* The following steps are required to properly configure the McASP via the OMAP-L138 McASP User's Guide
* [1] Reset McASP to default Values by writting GBLCTL = 0
*/ 


 /* Put McASP in Reset by programming the global control registers */
	//Keep all Tx Clocks in Reset
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST, RESET);	
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR, CLEAR);		
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST, RESET);		
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST, RESET);
	
	//Keep all Rx Clocks In Reset
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR, CLEAR);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST, RESET);


/* [2] Configure the McASP Audio FIFO.
 * 		[a] Write FIFO
 * 			 - If Write FIFO will not be enabled, clear the FIFO Enable Bit
 * 			 - If Write FIFO is enabled, it should not be enabled until all other FIFO 
 *             bits are configured
 * 		[b] Read FIFO
 * 			 - If Read FIFO will not be enabled, clear the FIFO Enable Bit
 * 			 - If Read FIFO is enabled, it should not be enabled until all other FIFO 
 * 
 */
 
 	/* Disable Write FIFO */
 		
 	// For now, both the Rx and Tx AFIFO's will be disabled, because the McASP is the only 
 	//peripheral that is being services by the DSP. If additional peripheral are added in later, 
 	//this may be changed to include both the Rx / Tx FIFO's	
 		
	//Disable Tx FIFO
	CSL_FINST(afifoRegs->WFIFOCTL, AFIFO_WFIFOCTL_WENA, DISABLED);
	
	//Disable Rx FIFO
	CSL_FINST(afifoRegs->RFIFOCTL, AFIFO_RFIFOCTL_RENA, DISABLED);
	
 
 /* [3] Configure all McASP registers except GBLCTRL in the following Order
  * 	[a] Receive Registers: If external clocks are used, they must be running already for proper synchronization
  *         of the global control registers
  * 		
  * 		Note:
  * 		TLV320AIC3106 is simply a slave ADC/DAC the Tx clocks will be synchronized with the Rx clocks. */
  
  
	/* Recieve Serializer */  	
  	/* 31   30    29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10      9        8      7       6    5     4    3     2     1   0 */                    
	/*MSb (MSb-1)        --Audio Word--                                          (LSb+1)  LSb    Mask     Mask Mask Mask  Mask  Mask Mask Mask */
  
  
  	/* Recieve Bit Stream Format Register */
	
	//Configure the receive bit stream for 32 bit I2S.
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RDATDLY, 1BIT);		//Ignore First Bit due to I2S
	
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RRVRS, MSBFIRST);
	
	//Pad Unused Bits with value in bit 0
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RPAD, ZERO);
	
	//32 bit slot size, though only 24 bit word size
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RSSZ, 32BITS);
	
	
	//No Rotation needed
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RROT, NONE);
	
	//Read XRBUF[n] on the Peripheral Configuration Port  (For Now -> May change to the DMA Later)
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RBUSEL, VBUS);
  
  
  
  
  
	/* Recieve Format Unit Bit Mask Register */
	
	//Mask Off Unused Bits -> For Now, well leave all unmasked -> May change later.
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK31, NOMASK);	//Audio Data MSB	
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK30, NOMASK);	//Audio Data MSB-1
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK29, NOMASK);   
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK28, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK27, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK26, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK25, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK24, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK23, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK22, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK21, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK20, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK19, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK18, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK17, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK16, NOMASK);	//Audio Data Bit LSB (16 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK15, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK14, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK13, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK12, NOMASK);	//Audio Data Bit LSB (20 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK11, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK10, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK9,  NOMASK);		
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK8,  NOMASK);	//Audio Data LSB (24 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK7,  NOMASK);		
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK6, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK5, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK4, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK3, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK2, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK1, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK0, NOMASK);
	
	

	

/* Receive Frame Sync Control Register */
	
	//Configure Frame Sync for 2 Channel TDM
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_RMOD, I2S);
	//Configure Frame Sync to last length of word
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FRWID, WORD);
	//Configure Frame Sync for internal generation
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRM, INTERNAL);
	//Configure Frame Sync that falling edge starts new channel for I2S
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRP, FALLINGEDGE);
	
	
	
	/* Receive Bit Clock Control Register */
	//Sample bit on Rising Edge of ACLKR
	CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRP, RISINGEDGE);
	//Clock Generated by OMAP-L138
	CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRM, INTERNAL);
	CSL_FINS(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRDIV, 0); 			//Irrelvant when ASYNC = 0
	
	
	/*Receive High Frequency Clock Control Register (Master Clock)*/
		//Irrelvant when ASYNC = 0
		
	/*Receive TDM Time Slot Register */
	//Slots 31-2 Inactive
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS31, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS30, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS29, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS28, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS27, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS26, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS25, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS24, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS23, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS22, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS21, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS20, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS19, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS18, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS17, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS16, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS15, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS14, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS13, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS12, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS11, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS10, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS9, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS8, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS7, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS6, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS5, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS4, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS3, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS2, INACTIVE);
	//Slots 0,1 Active for I2S
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS1, ACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS0, ACTIVE);
	
	/* Receiver Interrupt Control Register */

	//Disable Start of Frame Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSTAFRM, DISABLE);
	//Disable Data Read Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDATA, DISABLE);
	//Disable Recive Last Time Slot Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RLAST, DISABLE);
	//Disable DMA Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDMAERR, DISABLE);
	//Disable Clock Failure Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RCKFAIL, DISABLE);
	//Disable Unexpected FrameSync Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSYNCERR, DISABLE);
	//Disable Reciever Overrun Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_ROVRN, DISABLE);


  	//Recieve Clock Check Control Register
 		//Since Rx Clock is synchronized with Tx Clock, 
 		//No need to configure Rx Clock Check Circuit - because
 		//fail to Tx Clock will propogate in fail to Rx clock


  /* 	[b] Transmit Registers: If external clocks are used, they must be running already for proper synchronization
  *         of the global control registers */
  
  
  
  	/*Transmit Serializer */
	
	//Data Aligment Recieved from DSP -> Echo of McASP Rx
	/* 31      30    29    28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10   9       8      7     6 5 4 3 2 1 0 */                    
	/* Delay   MSb (MSb-1)                                                          LSb+1)  LSb  */

	//  ^
	//  |
	// (From I2S Protocol)		
	

  	/*Transmit Format Unit Bit Mask Register */
	//Keep All Bits unmaksed 
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK31, NOMASK);		//Audio Data Bit MSB
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK30, NOMASK);		//Audio Data Bit MSB-1	
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK29, NOMASK);			
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK28, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK27, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK26, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK25, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK24, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK23, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK22, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK21, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK20, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK19, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK18, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK17, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK16, NOMASK);		//Audio Data Bit LSB (16 bit)
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK15, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK14, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK13, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK12, NOMASK);		//Audio Data Bit LSB (20 bit)
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK11, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK10, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK9, NOMASK);		//Audio Data Bit LSB +1 
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK8, NOMASK);		//Audio Data Bit LSB (24 bit)	
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK7, NOMASK);				
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK6, NOMASK);			
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK5, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK4, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK3, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK2, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK1, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK0, NOMASK);
	
		
	
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XDATDLY,  0BIT);		//For Echo, McASP has already delayed the 1 bit, 
												//so for a direct copy, do not delay another bit
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XRVRS,    MSBFIRST);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XPAD, 	ZERO);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XSSZ, 	32BITS);
	CSL_FINS(mcaspRegs->XFMT, MCASP_XFMT_XPBIT, 	0);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XROT,	NONE);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XBUSEL, 	VBUS);	

	/*Transmit Frame Sync Control Register */
		//Frame Sync is configured for I2S
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_XMOD, I2S);
		//Frame Sync Length is Word
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FXWID, WORD);
		//Frame Sync is internally generated by XCLK
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXM, INTERNAL);
		//Falled Edige indicates beginning of new word
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXP, FALLINGEDGE);
	
	/* Transmit Clock Control Register */
	
	/* ACLKX = 3.072MHz = 64Fs = 256Fs/4 */
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXP, RISINGEDGE);
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_ASYNC, SYNC);				//ACLKR / nACLKX
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXM, INTERNAL);
	CSL_FINS(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXDIV, 7);
	
	
	/* Transmit High Frequency Clock Register*/
	// Generate High Frequency Clock Source Externally from 24.576MHz XTAL
	//CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXM, EXTERNAL);
	CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXM, INTERNAL); //PK
	CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXP, NOTINVERTED);
	
	// AHCLKX = 24.576MHz
	CSL_FINS(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXDIV, 0);
		
	
	

	/* Transmit TDM Time Slot Register */
	//32-2 should be inactive
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS31, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS30, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS29, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS28, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS27, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS26, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS25, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS24, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS23, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS22, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS21, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS20, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS19, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS18, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS17, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS16, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS15, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS14, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS13, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS12, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS11, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS10, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS9,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS8,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS7,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS6,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS5,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS4,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS3,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS2,  INACTIVE);
	//Active Slots 0/1 for I2S
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS1,  ACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS0,  ACTIVE);
	
	/*Transmit Interrupt Control Register */
	//Disable All Transmit McASP Interrupts
#if 0
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSTAFRM, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDATA,   ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XLAST,   DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XCKFAIL, DISABLE);		
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSYNCERR, DISABLE);		
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XUNDRN,  DISABLE);		
#endif
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSTAFRM, ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDATA, ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XLAST, ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDMAERR, ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XCKFAIL, ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSYNCERR, ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XUNDRN, ENABLE);

  
  	//Transmit Clock Check Control Register
  		
	//Set McASP Clock Zone Post Scaler
	
	//Note McASP is driven by SYSCLK2 which is SYSCLK/ which is a divide
	// by two of the main system clock 300/2 = (150MHz)
	CSL_FINST(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XPS, DIVBY4);
	
	//Set XMAX Value
		//Notes: Prescale by 4
		//150/4 = 37.5 MHz.
		
		//37.5MHz /24.576MHz (AUXCLK)  = 1.52587890625
		//32 Clock Counts * 1.52587890625 = 48.8 McASP System Clock Counts per every 32 AHCLKX
		//Counts
		
		//___________________________________________
		//32 ACLKs / 24.576MHz = 1.302uSec 
		
		//48 Clocks / 37.5 MHz = 1.28 uSec
		//49 Clocks / 37.5 MHz = 1.306uSec
		
		//___________________________________________
		//Check
		//1.28 uSec < 1.302uSec < 1.306uSec
		
		//Include clock count buffer of 1 CLOCK
		//So Configure XMIN to be Uint8 47 (0x2F)
		//   Configure XMAX to be Uint8 50 (0x32)
	
	CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMIN, 0x2F);	
	CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMAX, 0x32);

  	
  
  
  /* 

  * [c] Serializer Registers */
 		//We only care to configure those for Serialzer 11,12 in this example
 	 
 	 //Configure Serializer 11 to be a Transmit Serializer
  	CSL_FINST(mcaspRegs->SRCTL11, MCASP_SRCTL11_SRMOD, XMT);
  	 //Configure Serializer 13 to be a Transmit Serializer (digital loopback mode)
  	//CSL_FINST(mcaspRegs->SRCTL13, MCASP_SRCTL13_SRMOD, XMT);
  	
  	//Configure Serializer 12 to be a Recieve Serializer
	CSL_FINST(mcaspRegs->SRCTL12, MCASP_SRCTL12_SRMOD, RCV);
 
 
 /* 	[d] Global Registers: */
 
 		/* PFUNC Register */
			//Configure AHCLKX, ACLKX, AFSX, AXR11, AXR12 as McASP Pins vs. GPIO Pins
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AFSX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AHCLKX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_ACLKX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR11, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR12, MCASP);	


		/* PDIR Register */
		//Configure the AHCLKX, ACLKX, AFSX, AXR11 as Output Pins to send Clocks/Data from TLV320AIC3106
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSX, OUTPUT);
	//CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKX, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKX, OUTPUT);// PK
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKX, OUTPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR11, OUTPUT);

	
	//Configure AXR11 as Input to Get Data from TLV320AIC3106
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSR, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKR, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKR, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR12, INPUT);

/* Digital Interface Tranmistter Control Regiser */

	//Disable DIT Portion of McASP
	CSL_FINST(mcaspRegs->DITCTL, MCASP_DITCTL_DITEN, DISABLE);
	
/* Digital Loopback Control Register*/

	//Configure Digital Loopback
	CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_DLBEN, DISABLE);
	//CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_DLBEN, ENABLE);
	CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_ORD, XMTODD); // AXR11, Tx
	//CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_MODE, XMTCLK); // PK


	

	/* AMUTE Register */

/* The stat of this register doesn't matter on the OMAP-L138 baseboard
 * because the AMUTE pin is not connected to the TLV320AIC3106 Device */
 
	//Configure AMUTE Pin to drive when any Error Occurs
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XCKFAIL, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RCKFAIL, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);
	
	//Disable AMUTEIN Pin to isolate from LogicPD HW status
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INSTAT, INACTIVE);
	
	//Disable Drive on AMUTEOUT when AMUTEIN error is active
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INEN, DISABLE);
	
	//Configure AMUTE Input Logic Level to High
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INPOL, ACTHIGH);
	//Disable AMUTE PIN
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_MUTEN, DISABLE);
	
	
	/* Steps 4-11 Continued in McASPStart(); */

return;
}

void McASPStart(void){
	

 	/* [4] Start the respective High Frequency Serial Clocks
 	 * 		[a] Take the respective High Frequency Clocks out of reset
 	 *		[b] Read back from GBLTRL to ensure the bits to which you wrote are sucessfully latch in GBLCTL before you proceed
 	 */
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE){
 	 		
 	 		 //Start Transmit High Frequency clock if not active
 			 CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XHCLKRST, ACTIVE);
 			 
 			//Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE);	

 	 	}

 	 	
 	 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE){
 
 			//Start Recieve High Frequency clock
 	 	  	CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RHCLKRST, ACTIVE);
 	 	  	 
 	 	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE);
 	 	}

 	 
 	 /* [5] Start the respective serial clocks
 	  * 		[a] Take the respective internal serial clock dividers out of reset
 	  * 		[b] Read by from GBLCTL to ensure the bits to which you wrote are succesfully latched*/
 	  
		if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE){
 	 		
  		 	//Start Transmit High Frequency clock if not active
 		 	CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XCLKRST, ACTIVE);
 			 
 			//Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE);
 	 	}

 	 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RCLKRST, ACTIVE);
 	 	  	 
 	 	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE);
 	 	}

 	 	/* [6] Set Up data acquistion as required 
 	 	 * 		[a] If DMA is used to service the McASP, set up the data Acquisition as desired and start 
 	 	 *          the DMA
 	 	 * 		[b] If CPU interrupt is used to service the McASP, enable the transmit/recieve interrupt
 	 	 *          as required
 	 	 *      [c] If CPU pooling is used to service the McASP, no action is required in this step
 	 	 */
 	 	 
 	 	 	//For now we use CPU polling -> so no action is required
 	 	 	
 	 	 /* [7] Activate Serializers
 	 	  * 	[a] Before starting, clear the Tx/Rx Status registers by writting FFFF to them*/
 	 	
 	 	  	
 	 	  
 	 	  	mcaspRegs->XSTAT = 0x0000FFFF;
 	 	  	mcaspRegs->RSTAT = 0x0000FFFF;
 
 	 	  	
 	 	/*  	[b] Take the Serializers out of Reset
 	 	 * [c] Read back from GBLCTL to ensure the bits are latched  */  	
 	 	 
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSRCLR, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE);
 	 	} 
 	 	
 	  	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSRCLR, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE);
 	 	} 	 	  
 
 	 	 
		/* [8] Verify that Tx Buffers are services. 
		 * 		[a] If DMA is used to service the McASP, the DMA auto services the McASP upon
		 * 			recieving AXEVT. Before proceeding, you should verify that the XDATA in XSTAT is clear
		 *   		to zero, indicating that the Tx buffers are already services by the DMA 
		 * 
		 *		[b] If CPU interrupt is used to service the McASP, ISRs is entered upon the AXINT interrupt.
		 *    		The interrupt service routing should service the XBUF registers. Before proceeding, clear
		 * 			the XDATA bit in the XSTAT
		 * 
		 * 		[c] If CPU Pooling is used to service the McASP, the XBUF Registers should be written to in this
		 * 			step */

 	  	//mcaspRegs->XSTAT=0x00000020;  //b. XDATA bit is cleared by writing 1 to that bit
		 
		 	//Write Dummy Value of 0x00000000u to the XBUF11 (Tx Serializer)

		 
		 if(CSL_FEXT(mcaspRegs->XSTAT, MCASP_XSTAT_XDATA)==CSL_MCASP_XSTAT_XDATA_YES){
		 	mcaspRegs->XBUF11 = 0xAAAAAAAAu;
		 	//mcaspRegs->XBUF13 = 0x5555555Au;
		 }
		

		 	
		 
	

 /*[9] Release the State Machines from Reset */
 
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSMRST, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE);
 	 	}
 	 	
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSMRST, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE);
 	 	}
 
 




/* [10]. Release frame sync generators from reset. Note that it is necessary to release the internal frame sync
generators from reset, even if an external frame sync is being used, because the frame sync error
detection logic is built into the frame sync generator.
	a. Take the respective frame sync generator(s) out of reset by setting the RFRST bit for the receiver,
		and/or the XFRST bit for the transmitter in GBLCTL. All other bits in GBLCTL should be left at the
		previous state. 
	b. Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
		GBLCTL before you proceed. */



 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE){
  			//Start Recieve Serial Clock
  		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XFRST, ACTIVE);
  	  	 
  	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
  		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE);
  	}
  	
  	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE){
  			//Start Recieve Serial Clock
  		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RFRST, ACTIVE);
  	  	 
  	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
  		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE);
  	}

		






/* [11]. Upon the first frame sync signal, McASP transfers begin. The McASP synchronizes to an edge on the
frame sync pin, not the level on the frame sync pin. This makes it easy to release the state machine
and frame sync generators from reset.
a. For example, if you configure the McASP for a rising edge transmit frame sync, then you do not
need to wait for a low level on the frame sync pin

*/	
	

	
	

	return;	
}

void McASPStop(void){

	/* This function should be used to stop clocks in the reverse order
	 * from McASPStart */
	 
	return;	
}

void McASPEcho(void){
	/* This function is used to wait until a McASP Event comes in, 
	 * read the data and directly write it back out to the Codec */
	 
	 //Notes McASP Interrupts are still masked here so nothing should
	 //interrupt the CPU
	 
	 //RSYNC error is expected right away, but shouldn't occur after first event
	   		//because the clock references are internal and stable
  
 	return;
}

void McASPRestart(){
	
	if(mcaspRegs->GBLCTL == 0x00000000){
		
		McASPInit();
		McASPStart();
	}
	
	
}

//Project  Name: quickStartOMAPL1x McASP Chip Support Library Example
//Texas Instruments Device Platform: Logic Product Development OMAP-L138 Experimentor Kit
//Copywrite (c) 2011 Texas Instruments Incroporated


/*===============================================================*/
/****************************LICENSE *****************************/
/*===============================================================*/
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*/
 
 
 
 /*===============================================================*/
/***************************INCLUDES *****************************/
/*===============================================================*/ 
#include "dspmm.h"
#include "mcasp.h"


Uint8 TxClockFail = 0x00;
Uint8 TxDMAFail = 0x00;
Uint8 TxFrameFail = 0x00;
Uint8 TxUnderFail = 0x00;



CSL_DspintcRegsOvly dspintcRegs = (CSL_DspintcRegsOvly) 	CSL_INTC_0_REGS;
//CSL_IdmaRegsOvly 	dspdmaRegs 	= (CSL_IdmaRegsOvly)   	CSL_IDMA_0_REGS;
//Uint32Ovly 			dsppdnRegs 	= (Uint32Ovly) 		DSPPDC_BASE_ADDRESS;
CSL_CacheRegsOvly 	dspcache 	= (CSL_CacheRegsOvly) 	CSL_CACHE_0_REGS;


void DSPMMInit(void){
	
	DSPPowerdownInit();					//Initialize DSP Power
	DSPInit();							//Initialize DSP Control Registers
	DSPCacheInit();						//Initialize DSP Cache Controllers
	DSPIntCtrlInit();					//Initialize DSP Interrupt Controller
}



void DSPPowerdownInit (void)
{
	//Leave C674x MegaModule Power Down alone since it defaults to enabled.
}


//Configure DSP Core
void DSPInit(void){
	
/* === Addressing Mode Register ===*/
	   CSL_FINST(AMR, CHIP_AMR_BK0, RESETVAL);
	   CSL_FINST(AMR, CHIP_AMR_BK1, RESETVAL);
	   CSL_FINST(AMR, CHIP_AMR_B7MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_B6MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_B5MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_B4MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A7MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A6MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A5MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A4MODE, LINEAR);

/* === Control Status Reigster === */
//CSR;
	
		CSL_FINST(CSR, CHIP_CSR_PWRD, RESETVAL);		//Keep C674 Powered Up
		CSL_FINST(CSR, CHIP_CSR_EN, LITTLE );			//Configure as Little Endian
		CSL_FINST(CSR, CHIP_CSR_GIE, DISABLE );			//Disable Global Interrupts
	
/* === Interrupt Flag Reigster === */
//IFR;
		/* Keep Default */ 

/* === Interrupt SET Reigster === */
//ISR;
		/* Keep Default */ 
		
/* === Interrupt Clear Reigster === */
//ICR;

		//Apparently can cant write to ICR here?
//		CSL_FINST(ICR, CHIP_ICR_IC15, CLR );					//Clear Interrupts 15-4
//		CSL_FINST(ICR, CHIP_ICR_IC14, CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC13, CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC12, CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC11, CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC10, CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC9,  CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC8,  CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC7,  CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC6,  CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC5,  CLR );
//		CSL_FINST(ICR, CHIP_ICR_IC4,  CLR );

/* === Interrupt Enable Reigster === */
//IER;
		//Enable Non-Maskable
		CSL_FINST(IER, CHIP_IER_NMI, ENABLE );
	
		
		CSL_FINST(IER, CHIP_IER_IE04, ENABLE );				//Enable Interrupt 4 for McASP
		CSL_FINST(IER, CHIP_IER_IE05, DISABLE );			//Disable Interrupt 5
		CSL_FINST(IER, CHIP_IER_IE06, DISABLE );			//Disable Interrupt 6
		CSL_FINST(IER, CHIP_IER_IE07, DISABLE );			//Disable Interrupt 7
		CSL_FINST(IER, CHIP_IER_IE08, DISABLE );			//Disable Interrupt 8
		CSL_FINST(IER, CHIP_IER_IE09, DISABLE );			//Disable Interrupt 9
		CSL_FINST(IER, CHIP_IER_IE10, DISABLE );			//Disable Interrupt 10
		CSL_FINST(IER, CHIP_IER_IE11, DISABLE );			//Disable Interrupt 11
		CSL_FINST(IER, CHIP_IER_IE12, DISABLE );			//Disable Interrupt 12
		CSL_FINST(IER, CHIP_IER_IE13, DISABLE );			//Disable Interrupt 13
		CSL_FINST(IER, CHIP_IER_IE14, DISABLE );			//Disable Interrupt 14
		CSL_FINST(IER, CHIP_IER_IE15, DISABLE );			//Disable Interrupt 15

/* === Interrupt Service Table Reigster === */
//ISTP;
		/* Keep Default */ 

/* === Non-Maskable Interrupt Return Pointer Reigster === */
//IRP;
		/* Overwritten by DSP during Maskable ISR */

/* === Non-Maskable Interrupt Return Pointer Reigster === */
//NRP;
		/* Overwritten by DSP during Non-Maskable ISR */
	
}


//Configure DSP Cache Controllers
void DSPCacheInit(void)
{

/* === Configure Level 1 Program Cache ===*/

/* === Configure Level 1 Data Cache ===*/

/* === Configure Level 2 Cache ===*/




}


//Configure DSP Interrupt Controller
void DSPIntCtrlInit (void)
{

	//Configure the Interrupt Controller for the following Map
	//  Reset -> Reset
	//  McASP -> CPUINT4
	//  All Others Unused

/* ===Event Combiner ===*/
	//Event Combiner is not used because we simply don't need it.
	//However we should mask off all the events for good measure.
	
	dspintcRegs->EVTMASK[0] = (Uint32) (0xFFFFFFFFu);
	dspintcRegs->EVTMASK[1] = (Uint32) (0xFFFFFFFFu);
	dspintcRegs->EVTMASK[2] = (Uint32) (0xFFFFFFFFu);
	dspintcRegs->EVTMASK[3] = (Uint32) (0xFFFFFFFFu);
	
	
/* ===Interrupt Selector ===*/	
		//MCASP Interrupt will be send to CPU Interrupt # 4 (highest priority of available interrupts
		CSL_FINS(dspintcRegs->INTMUX1, DSPINTC_INTMUX1_INTSEL4, CSL_INTC_EVENTID_MCASP0INT);
		//All Other Interrupts will be disabled in the CPU


/* ===Exception Combiner ===*/
	//By default all the event inputs to the Exception Register as Masked off - so nothing to do here since
	//we don't want system events to interrupt McASP ISR

/* ===Advanced Event Generator Mux ===*/
	//Leave as Default



	//Change the Interrupt Service Table Pointer from ROM to RAM address 
	ISTP = (unsigned int) DSPintcVectorTable;

}



//Non-Maskable Interrupt Service Routine
interrupt void NMI_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");
}

//Maskable Interrupt #4 Service Routine
interrupt void INT4_ISR(void){
	

	Uint32 xstat_in;
	Uint32 rstat_in;


	/* Interrupt Service Routine used for Combined Rx/Tx Interrupts from  McASP */
	
	/* If more than one interrupt request becomes active in the same cycle, a single interrupt
	 * request is generated on the McASP porrt. Subsequent interrupt requests that become active 
	 * while the first interrupt request is outstanding do not immediatly generate a new request
	 * pulse on the McASP Interrupt Port
	 * 
	 * The Transmit interrupt is serviced with the CPU writtein to XSTAT. If any interrupt requests
	 * are active after the write, a new request is generated on the McASP tx Interrupt port*/
	
	
	//Disable Global Interrupts
	_disable_interrupts();	

	//Capture Snapshot of XSTAT /RSTAT at entry of ISR as these value will potentially change during the ISR
	xstat_in = mcaspRegs->XSTAT;
	rstat_in = mcaspRegs->RSTAT;


	/*=========================================*/
	/********* Tx/Rx Error Interrupts *********/
	/*=========================================*/

	if( (xstat_in & 0x00000100) | (rstat_in & 0x00000100) )       {
		//At least one error occured on the McASP, and we need to handle - possible reset McASP
		
	/**** XCLKFAIL ****/
		if( (xstat_in & 0x00000004) && (mcaspRegs->XINTCTL & 0x00000004) ){
			
			//XCLK Failed
			//This portion of the ISR should always get entered once per McASP Start/Restart, 
			//thus it is the first thing we check.
			
			//This interrupt is expected just after McASP Reset release.
			//This should be architected so that if that the McASP Times out after certain number of clock errors
			
			if(!TxClockFail){
				//If first slot this error occurs	
				TxClockFail++;					//Increment Counter
				mcaspRegs->XSTAT = 0x00000004;		//Clear Status Bit
			}
			else{
				//This is at least the 2nd time around for the clock to fail, thus
				//we should take some action
				
				//Mask off all other Interrupts except Tx Clock and timeout
				TxClockFail++;		//Increment Clock Fail Count
									
				if(TxClockFail >=0x02){
					
					
					
					//Assume clock is wacked, signal for McASP Restart in Main Idle Loop
					mcaspRegs->GBLCTL =  0x00000000;
					
					//Mask Off all Interrupts to the DSP Interrupt Controller to guarantee
					//idle loop will run at least once.
					mcaspRegs->RINTCTL = 0x00000000;
					mcaspRegs->XINTCTL = 0x00000000;
					
				}	
			}
		}
		/**** XUNDRN ******/
		if( (xstat_in & 0x00000001) && (mcaspRegs->XINTCTL & 0x00000001) ){
			//Serializer Underrun occured - > Data is set out on the Tx Serializer - so we must reset the McASP	
			
			//Under runs are only check once per time slot, and remains set until the DSP explicitly writes a 1
			//to the XUNDRN bit to clear the underun condition.
			//	[a] In DIT mode, a pair of BMC zeros is shifted out when an underrun occurs.
			//	[b] In TDM mode, a long stream of zeros are shifted out causing, the DAC's to 
			//	    mute. To Recover, reset the McASP and start again with the proper Initialization
		
			
			// Stop McASP frame synch gen, serializers, state machines, then mask off all interrupts
			//to guarantee that idle loop will reset McASP.
			
						
			//We missed transfering data to XBUF11, so something is catastophically wrong with our code
				mcaspRegs->GBLCTL =  0x00000000;
					
			//Mask Off all Interrupts to the DSP Interrupt Controller to guarantee
			//idle loop will run at least once.
				mcaspRegs->RINTCTL = 0x00000000;
				mcaspRegs->XINTCTL = 0x00000000;
			
			//Clear the error
			mcaspRegs->XSTAT = 0x00000001;
					
		}

		/******Unexpected SOF *******/
		if( (xstat_in & 0x00000002) && (mcaspRegs->XINTCTL & 0x00000002) ){
			//Unexpected Tx Framesync -> If we have the McASP Rx/Tx Configured identially, shouldn't occur	
			//See McASP User Guide for instruction of how to handle.
			
			//In TMD mode -> this shouldn't happen unless the external XTAL goes bad, which 
			//will cause a XCLK Fail error as well.
			
			//Frame Sync is no longer sync'd -> Restart McASP
			mcaspRegs->GBLCTL =  0x00000000;
					
			//Mask Off all Interrupts to the DSP Interrupt Controller to guarantee
			//idle loop will run at least once.
				mcaspRegs->RINTCTL = 0x00000000;
				mcaspRegs->XINTCTL = 0x00000000;
		
			//Clear the error
			mcaspRegs->XSTAT = 0x00000002;
		}
		/*******XDMAERROR ***/
		if(  (xstat_in & 0x00000080) && (mcaspRegs->XINTCTL & 0x00000008)    ) {
			//McASP Transmit DMA Error Occured
			
			//Occurs when DMA writes more words to the DMA port than it should.
			//Not using DMA -> so this is a don't care for now
				
			//DMA's are not in use, and this interrupt is disabled -> to abort if code gets here
				mcaspRegs->GBLCTL =  0x00000000;
					
			//Mask Off all Interrupts to the DSP Interrupt Controller to guarantee
			//idle loop will run at least once.
				mcaspRegs->RINTCTL = 0x00000000;
				mcaspRegs->XINTCTL = 0x00000000;

			//Clear the Error
			mcaspRegs->XSTAT = 0x00000080;
		}	
	}	
	else{
	//Check for previous detected error flags that need to be cleared
		if(TxClockFail || TxDMAFail || TxFrameFail || TxUnderFail){
			//Assume Clock has stabilized
			if(TxClockFail){
				TxClockFail = 0x00;					//Clear Clock Fail Flag
				
			}
			if(TxDMAFail){
				TxDMAFail = 0x00;
				
			}
			if(TxFrameFail){
				TxFrameFail = 0x00;
			
			}
			if(TxUnderFail){
				TxUnderFail = 0x00;
			}
		
			//Restore Interrupts
		}
	}
	
	
	/*=========================================*/
	/********* Tx Non-Error Interrupts *********/
	/*=========================================*/
	

/* Tx Start of Frame */
	if( (xstat_in & 0x00000040) && (mcaspRegs->XINTCTL & 0x00000080)){
		//Start of Frame Interrupt Received
		
		//Disabled
		mcaspRegs->XSTAT = 0x00000040;			//Clear Flag	
	}

	
	
/* Tx Data */
	if( (xstat_in & 0x00000020) && (mcaspRegs->XINTCTL & 0x00000020) ){
		//Tx Buffer is hungry for data
		 
		//Check to make sure RDATA buffer contains new data from XRSR12
		if((((rstat_in & 0x00000020) == 0x00000020) && ((rstat_in & 0x00000001) == 0x00000000 ))){
			mcaspRegs->XBUF11 = (Uint32) mcaspRegs->RBUF12;	
			//mcaspRegs->XBUF11 = (Uint32) 0x7FFFFFFF;


		}
		else{
			//RDATA is not new -> Transfer Zero's onto the bus for this Slot
			mcaspRegs->XBUF11 = 0x00000000u;	
		}
	
		mcaspRegs->XSTAT = 0x00000020;			//Clear Flag
	}
	

/* Tx XLAST */
	//Disabled as this would cause an interrupt every other frame

	
/* Tx TDM Slot */
	//Disabled as this would cause an interrupt every other frame
	
	
	/*=========================================*/
	/********* Rx Non-Error Interrupts *********/
	/*=========================================*/

	
/* Rx Start of Frame */
	//Disabled since Rx SOF is synchonrized with Tx SOF

/* Rx Data */
	//Disabled due to synchronization of Rx/Tx

/* Tx RLAST */
	//Disabled due to synchronization of Rx/Tx

/* Rx TDM Slot */
	//Disabled due to synchronization of Rx/Tx		



	//Re-Enable Global Interrupts
	_enable_interrupts();	
	
	



}

//Maskable Interrupt #5 Service Routine
interrupt void INT5_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");	
}

//Maskable Interrupt #6 Service Routine
interrupt void INT6_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");	
}

//Maskable Interrupt #7 Service Routine
interrupt void INT7_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");	
}

//Maskable Interrupt #8 Service Routine
interrupt void INT8_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");	
}

//Maskable Interrupt #9 Service Routine
interrupt void INT9_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");
}

//Maskable Interrupt #10 Service Routine
interrupt void INT10_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");	
}

//Maskable Interrupt #11 Service Routine
interrupt void INT11_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");	
}

//Maskable Interrupt #12 Service Routine
interrupt void INT12_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");
}

//Maskable Interrupt #13 Service Routine
interrupt void INT13_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");	
}

//Maskable Interrupt #14 Service Routine
interrupt void INT14_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");
}

//Maskable Interrupt #15 Service Routine
interrupt void INT15_ISR(void){
	asm(" B B3");			//Branch to Return Pointer Register
	asm(" NOP 5");
}

//*==================================================*/
//********************Includes *********************/
//*==================================================*/
//*Non-DSP/BIOS5 Header Files*/
#include <ti/pspiom/cslr/tistdtypes.h>
#include "mcasp.h"

//==================================================/
//***************Function Prototypes ***************/
//==================================================/
void McASPInit(void);
void McASPStart(void);
void McASPTx(void);
extern void Delay(volatile unsigned int delay);
//==================================================/
//*********Global Variable Instantiations **********/
//==================================================/

//McASP0 Control Registers
CSL_McaspRegsOvly mcaspRegs = (CSL_McaspRegsOvly) CSL_MCASP_0_CTRL_REGS;	//OMAP-L138 McASP Configuration Register Pointer Instance

//McASP AFIFO Control Registers
CSL_AfifoRegsOvly afifoRegs = (CSL_AfifoRegsOvly) CSL_MCASP_0_FIFO_REGS;

//McASP DMA Port Registers
CSL_AdataRegsOvly adataRegs = (CSL_AdataRegsOvly) CSL_MCASP_0_DATA_REGS;


//==================================================/
//**********Functions ******************************/
//* This function is used to initialize the McASP*/
//==================================================/


//OMAP-L138 Clocking Configuration
//AHCLKX -> Internal
//ACLKX  -> Internal / -> AHCLK/8
//AFSX   -> Interal -> Auto Generated by FS Gen.


void McASPInit(void)
{

/*This function will be called by Main to Initialize the McASP */
/* Although this configuration can be done completely by hand, we chose to use the
 * OMAP-L138 Chip Support Library (CSL) because those functions presumably already
 *  work and are tested*/


//Initialize the McASP Registers for use on the ESP board.

/* The following steps are required to properly configure the McASP via the OMAP-L138 McASP User's Guide
* [1] Reset McASP to default Values by writing GBLCTL = 0
*/


 /* Put McASP in Reset by programming the global control registers */
	//Keep all Tx Clocks in Reset
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR, CLEAR);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST, RESET);

	//Keep all Rx Clocks In Reset
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR, CLEAR);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST, RESET);


/* [2] Configure the McASP Audio FIFO.
 * 		[a] Write FIFO
 * 			 - If Write FIFO will not be enabled, clear the FIFO Enable Bit
 * 			 - If Write FIFO is enabled, it should not be enabled until all other FIFO
 *             bits are configured
 * 		[b] Read FIFO
 * 			 - If Read FIFO will not be enabled, clear the FIFO Enable Bit
 * 			 - If Read FIFO is enabled, it should not be enabled until all other FIFO
 *
 */

 	/* Disable Write FIFO */

 	// For now, both the Rx and Tx AFIFO's will be disabled, because the McASP is the only
 	//peripheral that is being services by the DSP. If additional peripheral are added in later,
 	//this may be changed to include both the Rx / Tx FIFO's

	//Disable Tx FIFO
	CSL_FINST(afifoRegs->WFIFOCTL, AFIFO_WFIFOCTL_WENA, DISABLED);

	//Disable Rx FIFO
	CSL_FINST(afifoRegs->RFIFOCTL, AFIFO_RFIFOCTL_RENA, DISABLED);


 /* [3] Configure all McASP registers except GBLCTRL in the following Order
  * 	[a] Receive Registers: If external clocks are used, they must be running already for proper synchronization
  *         of the global control registers
  *
  * 		Note:
  * 		TLV320AIC3106 is simply a slave ADC/DAC the Tx clocks will be synchronized with the Rx clocks. */


	/* Recieve Serializer */
  	/* 31   30    29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10      9        8      7       6    5     4    3     2     1   0 */
	/*MSb (MSb-1)        --Audio Word--                                          (LSb+1)  LSb    Mask     Mask Mask Mask  Mask  Mask Mask Mask */

	/* Recieve Format Unit Bit Mask Register */
#if 0
	//Mask Off Unused Bits -> For Now, well leave all unmasked -> May change later.
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK31, NOMASK);	//Audio Data MSB
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK30, NOMASK);	//Audio Data MSB-1
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK29, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK28, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK27, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK26, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK25, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK24, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK23, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK22, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK21, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK20, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK19, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK18, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK17, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK16, NOMASK);	//Audio Data Bit LSB (16 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK15, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK14, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK13, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK12, NOMASK);	//Audio Data Bit LSB (20 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK11, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK10, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK9,  NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK8,  NOMASK);	//Audio Data LSB (24 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK7,  NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK6, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK5, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK4, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK3, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK2, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK1, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK0, NOMASK);


  	/* Recieve Bit Stream Format Register */

	//Configure the receive bit stream for 32 bit I2S.
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RDATDLY, 1BIT);		//Ignore First Bit due to I2S

	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RRVRS, MSBFIRST);

	//Pad Unused Bits with value in bit 0
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RPAD, ZERO);

	//32 bit slot size, though only 24 bit word size
	//CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RSSZ, 32BITS);
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RSSZ, 24BITS);


	//No Rotation needed
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RROT, NONE);

	//Read XRBUF[n] on the Peripheral Configuration Port  (For Now -> May change to the DMA Later)
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RBUSEL, VBUS);



/* Receive Frame Sync Control Register */

	//Configure Frame Sync for 2 Channel TDM
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_RMOD, I2S);
	//Configure Frame Sync to last length of word
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FRWID, WORD);
	//Configure Frame Sync for internal generation
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRM, INTERNAL);
	//Configure Frame Sync that falling edge starts new channel for I2S
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRP, FALLINGEDGE);



	/* Receive Bit Clock Control Register */
	//Sample bit on Rising Edge of ACLKR
	CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRP, RISINGEDGE);
	//Clock Generated by OMAP-L138
	CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRM, INTERNAL);
	CSL_FINS(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRDIV, 0); 			//Irrelvant when ASYNC = 0


	/*Receive High Frequency Clock Control Register (Master Clock)*/
		//Irrelvant when ASYNC = 0

	   /*
	     * Receive Clock Check Control Register (RCLKCHK)
	     *  3         2         1
	     * 10987654321098765432109876543210
	     * 00000000........................ RCNT      ; R, receive clock count value
	     * ........00000000................ RMAX      ; RW, receive clock max boundary
	     * ................00000000........ RMIN      ; RW, receive clock min boundary
	     * ........................~~~~.... RESVD
	     * ............................0000 RPS       ; RW, 0 = McASP system clock divide by 1
	     */
	mcaspRegs->RCLKCHK = 0x00000000;



	/*Receive TDM Time Slot Register */
	//Slots 31-2 Inactive
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS31, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS30, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS29, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS28, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS27, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS26, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS25, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS24, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS23, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS22, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS21, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS20, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS19, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS18, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS17, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS16, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS15, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS14, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS13, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS12, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS11, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS10, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS9, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS8, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS7, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS6, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS5, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS4, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS3, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS2, INACTIVE);
	//Slots 0,1 Active for I2S
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS1, ACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS0, ACTIVE);

	/* Receiver Interrupt Control Register */

	//Disable Start of Frame Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSTAFRM, DISABLE);
	//Disable Data Read Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDATA, DISABLE);
	//Disable Recive Last Time Slot Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RLAST, DISABLE);
	//Disable DMA Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDMAERR, DISABLE);
	//Disable Clock Failure Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RCKFAIL, DISABLE);
	//Disable Unexpected FrameSync Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSYNCERR, DISABLE);
	//Disable Reciever Overrun Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_ROVRN, DISABLE);


  	//Recieve Clock Check Control Register
 		//Since Rx Clock is synchronized with Tx Clock,
 		//No need to configure Rx Clock Check Circuit - because
 		//fail to Tx Clock will propogate in fail to Rx clock

#endif
  /* 	[b] Transmit Registers: If external clocks are used, they must be running already for proper synchronization
  *         of the global control registers */



  	/* Recieve Serializer */

	//Data Aligment Recieved from DSP -> Echo of McASP Rx
	/* 31      30    29    28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10   9       8      7     6 5 4 3 2 1 0 */
	/* Delay   MSb (MSb-1)                                                          LSb+1)  LSb  */

	//  ^
	//  |
	// (From I2S Protocol)

  	/*Transmit Format Unit Bit Mask Register */
	//Keep All Bits unmaksed
#if 0
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK31, NOMASK);		//Audio Data Bit MSB
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK30, NOMASK);		//Audio Data Bit MSB-1
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK29, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK28, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK27, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK26, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK25, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK24, NOMASK);
#endif
	// It does not matter
	// Masking 8-MSB bits for 24-bit data
	// We get the same data even if they are not masked
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK31, MASK);		//Audio Data Bit MSB
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK30, MASK);		//Audio Data Bit MSB-1
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK29, MASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK28, MASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK27, MASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK26, MASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK25, MASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK24, MASK);

	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK23, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK22, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK21, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK20, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK19, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK18, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK17, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK16, NOMASK);		//Audio Data Bit LSB (16 bit)
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK15, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK14, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK13, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK12, NOMASK);		//Audio Data Bit LSB (20 bit)
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK11, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK10, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK9, NOMASK);		//Audio Data Bit LSB +1
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK8, NOMASK);		//Audio Data Bit LSB (24 bit)


	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK7, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK6, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK5, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK4, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK3, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK2, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK1, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK0, NOMASK);


	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XDATDLY,  1BIT);		//For I2S, MSB First, Left aligned, XATDLY=1

	//CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XDATDLY,  0BIT);		//For Echo, McASP has already delayed the 1 bit,
																	//so for a direct copy, do not delay another bit
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XRVRS,    MSBFIRST);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XPAD, 	ZERO);
	//CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XSSZ, 	32BITS);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XSSZ, 	24BITS); //PK
	CSL_FINS(mcaspRegs->XFMT, MCASP_XFMT_XPBIT, 	0);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XROT,	NONE);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XBUSEL, 	VBUS);//=1 for peripheral config bus
	//CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XBUSEL, 	VBUSP);//for DMA,=0



	/*Transmit Frame Sync Control Register */
	// This is all we can do to configure AFSX

	// Transmit frame sync mode select bits.
	//Frame Sync is configured for I2S (2-slot TDM (I2S mode) to 32-slot TDM)
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_XMOD, I2S);		//=2

	//Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during
	//its active period.
	//Frame Sync Length is Word (=1)
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FXWID, WORD);

	//Transmit frame sync generation select bit.
	//Frame Sync is internally generated by XCLK (=1)
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXM, INTERNAL);

	//Transmit frame sync polarity select bit.
	//Falling Edge indicates beginning of new word (=1)
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXP, FALLINGEDGE);


	/* Transmit Clock Control Register */

	//Transmit bit stream clock polarity select bit.
	//Rising edge. External receiver samples data on the falling edge of the serial clock, so the transmitter
	// must shift data out on the rising edge of the serial clock. (=0)
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXP, RISINGEDGE);

	//Transmit/receive operation asynchronous enable bit.
	// Synchronous. Transmit clock and frame sync provides the source for both the transmit and receive (=0)
	//sections. Note that in this mode, the receive bit clock is an inverted version of the transmit bit clock.
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_ASYNC, ASYNC);				//ACLKR / nACLKX

	//Transmit bit clock source bit.
	// Internal transmit clock source from output of programmable bit clock divider (=1)
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXM, INTERNAL);

	//Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX.
	// This ratio decides Fs
	// for Fs=192k, AHCLKX=128*Fs, ACLKX=48*Fs, AHCLKX/ACLKX=2.666(2)
	CSL_FINS(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXDIV, 1);


	/* Transmit High Frequency Clock Register*/
	// Generate High Frequency Clock Source Externally from 25 MHz XTAL (AUXCLK)
	//Transmit high-frequency clock source bit.
	CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXM, INTERNAL);

	//Transmit bitstream high-frequency clock polarity select bit.
	//Not inverted. AHCLKX is not inverted before programmable bit clock divider. (=0)
	CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXP, NOTINVERTED);

	// AUXCLK = 25MHz
	//Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to
	//AHCLKX.; 0 Divide-by-1
	// for Fs=192k, AHCLKX=128*Fs, ACLKX=48*Fs, AUXCLK/AHCLKX=1
	CSL_FINS(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXDIV, 0);



	/* Transmit TDM Time Slot Register */
	//32-2 should be inactive
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS31, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS30, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS29, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS28, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS27, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS26, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS25, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS24, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS23, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS22, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS21, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS20, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS19, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS18, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS17, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS16, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS15, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS14, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS13, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS12, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS11, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS10, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS9,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS8,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS7,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS6,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS5,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS4,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS3,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS2,  INACTIVE);
	//Active Slots 0/1 for I2S
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS1,  ACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS0,  ACTIVE);


	/*Transmit Interrupt Control Register */

	//Disable All Transmit McASP Interrupts
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSTAFRM, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDATA,   DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XLAST,   DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XCKFAIL, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSYNCERR, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XUNDRN,  DISABLE);

    /*
     * Setup the Xmit clock check register
     */


    //Transmit Clock Check Control Register

	//Set McASP Clock Zone Post Scaler

	//Note McASP is driven by SYSCLK2 = (375/2=187.5MHz)
	CSL_FINST(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XPS, DIVBY4); //XPS=2

	//Set XMAX Value
	//Notes: Prescale by 4
	//187.5/4 = 46.875 MHz.

	//46.875MHz /25MHz (AUXCLK)  = 1.875
	//24 Clock Counts * 1.875 = 45 McASP System Clock Counts per every 24 AHCLKX


	//___________________________________________
	//24 ACLKs / 25MHz = 0.96uSec

	//44 Clocks / 46.875 MHz = 0.94uSec
	//46 Clocks / 46.875 MHz = 0.98uSec

	//___________________________________________
	//Check
	//0.94 uSec < 0.96uSec < 0.98uSec

	//Include clock count buffer of 1 CLOCK
	//So Configure XMIN to be Uint8 44 (0x2C)
	//   Configure XMAX to be Uint8 46 (0x2E)

	CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMIN, 0x2C);
	CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMAX, 0x2E);



  /*

  * [c] Serializer Registers */

	//Configure Serializer 8, 15 to be Transmit Serializers
  	mcaspRegs->SRCTL8 = 0x0000001D;
  	mcaspRegs->SRCTL15 = 0x0000001D;
  	//mcaspRegs->SRCTL8 = 0x00000019;
  	//mcaspRegs->SRCTL15 = 0x00000019;

 /* 	[d] Global Registers: */

 		/* PFUNC Register */
	//Configure AHCLKX, ACLKX, AFSX, AXR8, AXR15 as McASP Pins or GPIO Pins
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AFSX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AHCLKX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_ACLKX, MCASP);

	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR8, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR15, MCASP);


	// PDIR Register
	//Configure the AHCLKX, ACLKX, AFSX, AXR8 and AXR15 as Output Pins

	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSX, OUTPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKX, OUTPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKX, OUTPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR15, OUTPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR8, OUTPUT);

/* Digital Interface Tranmistter Control Regiser */

	//Disable DIT Portion of McASP
	CSL_FINST(mcaspRegs->DITCTL, MCASP_DITCTL_DITEN, DISABLE);

/* Digital Loopback Control Register*/

	//Configure Digital Loopback
	CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_DLBEN, DISABLE);
	CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_ORD, XMTODD);




	/* AMUTE Register */

/* The stat of this register doesn't matter on the OMAP-L138 baseboard
 * because the AMUTE pin is not connected to the TLV320AIC3106 Device */

	//Configure AMUTE Pin to drive when any Error Occurs
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XCKFAIL, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RCKFAIL, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);

	//Disable AMUTEIN Pin to isolate from LogicPD HW status
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INSTAT, INACTIVE);

	//Disable Drive on AMUTEOUT when AMUTEIN error is active
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INEN, DISABLE);

	//Configure AMUTE Input Logic Level to High
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INPOL, ACTHIGH);
	//Disable AMUTE PIN
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_MUTEN, DISABLE);


	/* Steps 4-11 Continued in McASPStart(); */

return;
}

void McASPStart(void){


 	/* [4] Start the respective High Frequency Serial Clocks
 	 * 		[a] Take the respective High Frequency Clocks out of reset
 	 *		[b] Read back from GBLTRL to ensure the bits to which you wrote are sucessfully latch in GBLCTL before you proceed
 	 */
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE){

 	 		 //Start Transmit High Frequency clock if not active
 			 CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XHCLKRST, ACTIVE);

 			//Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE);

 	 	}

#if 0
 	 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE){

 			//Start Recieve High Frequency clock
 	 	  	CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RHCLKRST, ACTIVE);

 	 	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE);
 	 	}
#endif

 	 /* [5] Start the respective serial clocks
 	  * 		[a] Take the respective internal serial clock dividers out of reset
 	  * 		[b] Read by from GBLCTL to ensure the bits to which you wrote are succesfully latched*/

		if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE){

  		 	//Start Transmit High Frequency clock if not active
 		 	CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XCLKRST, ACTIVE);

 			//Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE);
 	 	}
#if 0
 	 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE){

 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RCLKRST, ACTIVE);

 	 	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE);
 	 	}
#endif
 	 	/* [6] Set Up data acquistion as required
 	 	 * 		[a] If DMA is used to service the McASP, set up the data Acquisition as desired and start
 	 	 *          the DMA
 	 	 * 		[b] If CPU interrupt is used to service the McASP, enable the transmit/recieve interrupt
 	 	 *          as required
 	 	 *      [c] If CPU pooling is used to service the McASP, no action is required in this step
 	 	 */

 	 	 	//For now we use CPU polling -> so no action is required

 	 	 /* [7] Activate Serializers
 	 	  * 	[a] Before starting, clear the Tx/Rx Status registers by writting FFFF to them*/



 	 	  	mcaspRegs->XSTAT = 0x0000FFFF;
 	 	  	//mcaspRegs->RSTAT = 0x0000FFFF;


 	 	/*  	[b] Take the Serializers out of Reset
 	 	 * [c] Read back from GBLCTL to ensure the bits are latched  */

 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE){

 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSRCLR, ACTIVE);

 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE);
 	 	}
#if 0
 	  	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE){

 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSRCLR, ACTIVE);

 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE);
 	 	}
#endif

		/* [8] Verify that Tx Buffers are services.
		 * 		[a] If DMA is used to service the McASP, the DMA auto services the McASP upon
		 * 			recieving AXEVT. Before proceeding, you should verify that the XDATA in XSTAT is clear
		 *   		to zero, indicating that the Tx buffers are already services by the DMA
		 *
		 *		[b] If CPU interrupt is used to service the McASP, ISRs is entered upon the AXINT interrupt.
		 *    		The interrupt service routing should service the XBUF registers. Before proceeding, clear
		 * 			the XDATA bit in the XSTAT
		 *
		 * 		[c] If CPU Pooling is used to service the McASP, the XBUF Registers should be written to in this
		 * 			step */


		 	//Write Dummy Value to the XBUF15 (Tx Serializer)


		 if(CSL_FEXT(mcaspRegs->XSTAT, MCASP_XSTAT_XDATA)==CSL_MCASP_XSTAT_XDATA_YES){
		 	mcaspRegs->XBUF15 = 0x555555u;
		 }



 /*[9] Release the State Machines from Reset */

 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE){

 			//Start Transmit Serial Clock
 	 		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSMRST, ACTIVE);

 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE);
 	 	}
#if 0
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE){

 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSMRST, ACTIVE);

 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE);
 	 	}
#endif




/* [10]. Release frame sync generators from reset. Note that it is necessary to release the internal frame sync
generators from reset, even if an external frame sync is being used, because the frame sync error
detection logic is built into the frame sync generator.
	a. Take the respective frame sync generator(s) out of reset by setting the RFRST bit for the receiver,
		and/or the XFRST bit for the transmitter in GBLCTL. All other bits in GBLCTL should be left at the
		previous state.
	b. Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
		GBLCTL before you proceed. */



 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE){
  			//Start Recieve Serial Clock
  		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XFRST, ACTIVE);

  	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
  		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE);
  	}
#if 0
  	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE){
  			//Start Recieve Serial Clock
  		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RFRST, ACTIVE);

  	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
  		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE);
  	}
#endif








/* [11]. Upon the first frame sync signal, McASP transfers begin. The McASP synchronizes to an edge on the
frame sync pin, not the level on the frame sync pin. This makes it easy to release the state machine
and frame sync generators from reset.
a. For example, if you configure the McASP for a rising edge transmit frame sync, then you do not
need to wait for a low level on the frame sync pin

*/



	return;
}
// This routine is called from main, in a while(1) loop
// This is a simple CPU polling routine to check the data on AXR15 pin
void McASPTx(){

 	if(mcaspRegs->XSTAT & 0x00000020){
	 	mcaspRegs->XBUF15 = 0x333333u;
	 	mcaspRegs->XSTAT = 0x00000020;
 	}
}

void McASPStop(void){

	/* This function should be used to stop clocks in the reverse order
	 * from McASPStart */

	return;
}

void McASPEcho(void){
	/* This function is used to wait until a McASP Event comes in,
	 * read the data and directly write it back out to the Codec */

	 //Notes McASP Interrupts are still masked here so nothing should
	 //interrupt the CPU

	 //RSYNC error is expected right away, but shouldn't occur after first event
	   		//because the clock references are internal and stable

 	return;
}

void McASPRestart(){

	if(mcaspRegs->GBLCTL == 0x00000000){

		McASPInit();
		McASPStart();
	}


}