SDRAM question in OMAP-L138

Stephen Lin said:

From the 1st page of OMAP-L138 spec under the "Two External Interfaces/EMIFA" section, it stated 16-Bit SDRAM with 128MB address space. However, in Table 6-18, it shows the max SDRAM goes up to 512MB (with two SDRAM loads). Why the discrepency (128MB vs 512MB)?  Is it because 512MB can only be allowed if freq scale down to 100Mhz??

This appears to be a typo in the data sheet.  The first reference should say 512MB since is the max SDRAM density the EMIFA can support.

Stephen Lin said:

Is SDRAM operating at 3.3v range only? Can it run at 1.8v? Looking at all its control lines from spec, it's can be powered from either 3.3v or 1.8v.

EMIFA pins can operate at both 3.3V and 1.8V.

Stephen Lin said:

In the case where one needs to put two external SDRAM (both at 256MB) to reach 512MB, does it affect the multiplexing feature of the chip where some control needs to be setup properly in order for two chips to work at the same time? If so, where in the spec does it mention this?

No, the EMIFA would not "know" there is more than on memory on the bus.  In the two-chip case you are referring to both memories would share all the controls signals, but one memory would drive the lower 8-bits of the bus on the other would drive the upper 8-bits of the bus.

Thanks for the quick detail answers.

For Question #2 listed above, you mention EMIFA can operate at both 3.3V and 1.8V, but SDRAM can only be running at 3.3v. There are no SDRAM module out there that can run under 1.8V?  That is why we are curious how can EMIFA interface to SDRAM using 1.8V, and mSDRAM is not supported (listed from spec).  Please advise. thanks.

Let me clarify.  The EMIFA pins can run at both 1.8 and 3.3V.  However, the voltage you use depends on what is supported on the device you are interfacing to.  You are correct that the EMIFA only supports SDRAM, and, unless there is a 1.8V SDRAM out there, you would have to run at 3.3V.  However, the EMIFA pins are also muxed with GPIO and PRU pins for which 1.8V operation is useful.

Hi

A minor clarification on #1, IMHO we deliberately put 128 MB on the first page, this was to correlate well with Table 6-18 , which highlights the fact that even though you have a device memory map that allows you to go upto 512MBytes, there are no SDRAM memory configuration as far as we know available, that will allow you to go upto 512 MBytes.

From an end user stand point, it is important to understand that the current memories available out in the market, only lets you go upto 128 MBytes overall on EMIFA SDRAM.

If we/you find any memories that lets you go higher then 128 MBytes, then we could definitely update the feature list on the 1st page.

Regards

Mukul

Ok, make sense on 128MB instead of 512MB because of the market availability.

On the same note, 16-bit DDR2 SDRAM is spec at 512MB (but didn't show the memory table). Does it mean that its configuration setting is not limited by the design, hence all DDR2 memory that has capacity of 512MB can be used. Please confirm. thanks.

Hi Stephen

Yes you should be able to find memories that allow you to hook up upto 512 MBytes for DDR2 or 256 MBytes for mDDR. The only limitation is that you are only allowed to a 1x16 or  2x8 memory configuration (as specified in the datasheet, see snapshot below), a 4x4 memory configuration is not allowed and recommended. 

Please note the intention of Table 6-18 highlights the memory density assuming maximum number of row bits are used, if your memory requires a smaller number of row bits, the memory density shown in the spreadsheet might not match up. The idea of the table was to show maximum addressability, assuming max row bits. This might not be clear from the table and we plan to put another footnote to clarify this.

I believe, we plan to put a similar table for DDR2/mDDR in the next revision of the datasheet

Regards

Mukul

--

OMAPL138 datasheet, Section 6.11.3.2 (Pg 117)

Table 6-26 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR-400 speed grade DDR2/mDDR devices. The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one
chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most controlsignals are shared just like regular dual chip memory configurations.

hi,

Yes you should be able to find memories that allow you to hook up upto 512 MBytes for DDR2 or 256 MBytes for mDDR. The only limitation is that you are only allowed to a 1x16 or  2x8 memory configuration (as specified in the datasheet, see snapshot below), a 4x4 memory configuration is not allowed and recommended.

it's seems that for a 512MBytes DDR2 only 1x16 is supported because 4Gb DDR2 has 15 bit address and the OMAPL138 has only 14 bit address.

Please advice how to connect a 512MBytes DDR2 to the processor.

Hi Jonathan

You are right that as per the JEDEC spec and memories available in the market today, you can only go upto 256Mbytes of memory with 14 Address lines as is the case with OMAPL138/AM18xx devices. Most of the memories out there require 15 address lines to get to 512MBytes configuration.

However, the datasheet comment was put in place just to show the device capability in terms of the number of address lines available and row/column calculations (shown below), not knowing if there is any lone vendor who could possibly be offering something with 14 address lines or any unknown roadmap offering from DDR2 vendor (none to my knowledge as of now).