a question about loading .out file

armin neamati

Other Parts Discussed in Thread: TMS320C6678, UCD9222

Hi to everyone

I built a board with using TMS320C6678 DSP core. I can connect to the core but when i want to load .out file, i face this error:

C66xx_0: GEL: File: D:\CCS_workspace\test6.out Does not match the target endianness, not loaded. Check project build options and target configuration file (ccxml)

Also i am using the XDS100V2 JTAG emulator and i define this JTAG with new target configuration. can you tell me what this error mean?!

thanks all

over 11 years ago

0 Ganapathi Dhandapani95 over 11 years ago

TI__Mastermind 28085 points

Hi Armin,

I think you have select little endian mode mode switch on target board and try to load big endian binary .out file to your target.

Please share your project file and EVM boot mode switch setting detail.

Thanks,

0 armin neamati over 11 years ago in reply to Ganapathi Dhandapani95

Expert 1595 points

I want to write some data to DSP and show on the console box. I try both state big and endian mode. Actually i want to know how can i boot the 6678 core?

0 Ganapathi Dhandapani95 over 11 years ago in reply to armin neamati

TI__Mastermind 28085 points

Hi Armin,

Please take a look at MCSDK User guide.

http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide

Thanks,

0 Raja over 11 years ago in reply to Ganapathi Dhandapani95

TI__Guru* 81335 points

Hi Armin,

Are you working on custom board or EVM?

If EVM, please refer below link for hardware setup.

http://processors.wiki.ti.com/index.php/TMDXEVM6678L_EVM_Hardware_Setup

With the MCSDK UG link provided above post, you shall import/create new projects and build and program your own images on to target.

Also refer the boot loader user guide for keystone I devices.

http://www.ti.com/lit/sprugy5

Thank you.

0 armin neamati over 11 years ago in reply to Raja

Expert 1595 points

Hi Rajasekaran

I am working with my custom board. I built a new one without using UCD9222. Also i use a virtex6 not spartan.

I observe the power sequence with LTM4627 and control the reset sequence with virtex6. When i connect smart reflex to the board, i can connect to board in CCS V5.5 but i can not load any .out file to my core. I don't know what i must do for programming the DSP?

0 Raja over 11 years ago in reply to armin neamati

TI__Guru* 81335 points

Hi Armin,

Are you able to load .out files successfully?

Please start new thread for difference issues. I could not see the update for the suggestion provided for the original issue reported in this thread.

Thank you.

0 armin neamati over 11 years ago in reply to Raja

Expert 1595 points

Hi Rajasekaran

unfortunately i can not load .out files to cores. I don't know what i must do?!!

Thank you

0 Ganapathi Dhandapani95 over 11 years ago in reply to armin neamati

TI__Mastermind 28085 points

Hi Armin,

Please share your test project file, gel file and target configuration file.

Thanks,

0 armin neamati over 11 years ago in reply to Ganapathi Dhandapani95

Expert 1595 points

Hi Ganapathi

I don't use special project. i want to load "HelloWorld" project with set registers. do you know how can i set the registers like GPIO registers?

0 Ganapathi Dhandapani95 over 11 years ago in reply to armin neamati

TI__Mastermind 28085 points

Hi Armin,

Please take a look at below wiki link for GPIO registers configuration

http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide#Example_1_-_Building_and_running_a_simple_single_core_application

Thanks,

0 Raja over 11 years ago in reply to Ganapathi Dhandapani95

TI__Guru* 81335 points

Hi Armin,

We understand that you have resolved the out file loading issue from your previous post. Hence closing this thread.

Thank you.

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a question about loading .out file