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DM365: clarification on PRTC Subsystem needed

I'm not using RTC in my design, but I want to use GPIO pins of PRTC subsystem. What should be the right combination of PWRST and PWRCNTON signals in order for that to work? I want the DM365 stay in external reset mode, i.e. without the PRTCSS sequence started.

 

Thanks.

  • So do I, I want to get the answer,too.

  • I suspect that in order to enable GPIO pins of RTCSS but keep it from going into "normal mode" I have to set PWRST to high, but keep PWRCNTON low. Can anyone at TI confirm this, please?

  • We were able to successfully use the PRTCSS in "external reset mode" (SPRUFJ0A 1.4.2) by setting PWRST low and PWRCNTON high.

    However, we found that the GPIO's direction are inverted in the GIO_DIR register description in the manual (SPRUFJ0A 4.2.3.)   The direction appears to use 0 for input and 1 for output.

  • -Confirmed Pete's assertion on section 1.4.2.

    Also,

    some similar topic was discussed in this particular post which might help. https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/p/42170/148608.aspx#148608 

    There are two documentation discrepancies in the guide.

    1) GO_OUT PINS: By default this pins are Output and are driven Low. (The PRTCSS Guide says default value is ‘driven high’ section 4.2.1 PRTCSS guide, but this the default is 'driven low'. The default value of GO_OUT register is not correct and it should be all '0' value).

    2) GIO_DIR PINS: By default this pins are Inputs and the value of the register = '0'. (The PRTCSS Guide register description description should be 0 for input and 1 for output. As peter found out.

    We will be making this modifications to the userguide in the next revision.

    regards,

    miguel

  • Hello Everyone,

     

    I too plan to boot the DM365 in "external reset mode" and will be setting PWRST low and PWRCNTON high. In this mode, other posters have shown the GPIO to be usable. My question is two-fold:

    1. Will the GIO inputs to the PRTCSS still function as interrupts in this mode? Essentially, we are trying to use the PRTCSS GIO interrupt-capable inputs to increase the number of interrupt-capable IO that go directly to the ARM. As per ARM Subsystem user guide SPRUFG5A table 54, we plan to use PWRGIO[2:0] as input interrupts.

    2. Since we don't need the calendar function, we'll leave the 32.768kHz crystal disconnected. We will connect RTCXI to GND, RTCXO will float, but where do we connect the VSS_32k pin?

     

    Many thanks,

    Mike

  • Hi Miguel,

    I am unsure how to address the PRTC registers as the ARM memory map give PRTCIF address as 0x01C69000 and the DM365 datasheet gives PRTCSS address as 0x01C69000 but in sprufjoa it looks like it's 2 different registers as the tables gives same offsets for different attributes?  I want to use PWCTRIO0 on my evmdm365 as user input to the sw2 it is wired to.

    Thanks, Jinh T.