- What is the clock frequency limit of the cpdma bus, for both 6441 and 6446-800?
- Is cpdma clock rate the same as SYSCLK2?
- If SYSCLK2 is set beyond 225MHz, can DSP side still access the 4KB VICP memory starting from 0x11112000?
-
Ask a related question
What is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.