What is the regn, regm and m4reg+1

ryan zhou

Hello:

When I modified the linux kernel about the DSI part, I am not quite clear about the meaning of regn, regm and m4reg+1. Is there someone can give me an short introduction about them and how to calculate them.

Regards

Ryan

over 12 years ago

0 Yordan Kovachev over 12 years ago

TI__Guru**** 161600 points

Hi Ryan,

Those are DPLL_VIDEOx divider factors: N (REGN), M (REGM) and Divider value for clock source (M4REG)

They are described in OMAP5432 TRM Subsection 10.3.4.5.10 DSI PLL Clock Sequence.

To get familiar with DSS PLLs and DSS clock structure you should glance at the whole Section 10.3.4.5 DSI PLL Controllers.

Best Regards,
Yordan

0 ryan zhou over 12 years ago in reply to Yordan Kovachev

Prodigy 220 points

Hi Yordan

Could you give me a link about the document include 10.3.4.5.10 DSI PLL Clock Sequence? thank you very much.

Regards

Ryan

0 Yordan Kovachev over 12 years ago in reply to ryan zhou

TI__Guru**** 161600 points

Hi Ryan,

For some reason it is not visible in the OMAP5432 product folder (http://www.ti.com/product/OMAP5432/technicaldocuments)... My guess is this is some technical issue with TI website.

Let me confirm that with TRM team management.

Best Regards,
Yordan

0 Yordan Kovachev over 12 years ago in reply to Yordan Kovachev

TI__Guru**** 161600 points

Hi Ryan,

I got feedback, that this should indeed be issue with the website. I alerted the appropriate teams.

Meanwhile please find attached only the DSS chapter from OMAP5432 TRM (I couldn't share the whole TRM, because it exceeds the max file size, that can be attached): 4338.CH10_DISPLY_543x_Public.pdf

Sections are renamed to 1.3.4.5.10 DSI PLL Clock Sequence & Section 1.3.4.5 DSI PLL Controllers.

Best Regards,
Yordan

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What is the regn, regm and m4reg+1