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am335x - phy-sel not independent for each slave?

Dear Sirs and Madam,


I'm wondering about doing a phy-sel independent for each slave.

The first Slave should run in RGMII mode, but the second one in RMII mode with external clock input.

As I can follow the code, the phy-sel node is a child of the cpsw-node so the properties entered in the phy-sel node are applied to both slaves.

Is there any posibility to getting this independent?

Thanks in advance.

Best Regards

Pascal Speck

  • Hi Pascal,

    Are you referring to the PHYs as slaves, as I'm not really sure I understand your question?

    Which version of the Sitara SDK are you using?

    Best regards,
    Miroslav

  • Hi Miroslav,

    sorry for this inconcrete expression. As "slaves" i mean the two CPSW-Ports of the AM335x.
    To clarify I'll sketch you my hardware setup:

    ---

    FPGA --------RGMII------------
                                  \
                                   \
                                   AM335x
    PHY A ---                      /
              \                   /
               KSZ8863RLL --RMII--
        < - This one should use external clock
              /
    PHY B ---

    Another question of mine is, how I can use "fixed-links" without respect to the Phy Port status within CPSW.
    Because neither the FPGA nor the RMII connection will change in Linkspeed or Duplex settings.
    Within Freescale or Broadcom there is a "fixed-link" dummy phy, which has actually no bindings to the cpsw.


    I'm using SDK 07.00.00.00

    Best Regards

    Pascal Speck

  • I've asked the factory team to help with this one. I will let you know as soon as I have an answer.

    Best regards,
    Miroslav

  • Are there any news for using a Fixed Link with the CPSW Driver?

    We need this behaviour for a trade show in the next weeks, so it would be nice if you have any hints for me.

    Best Regards

    Pascal Speck