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How does EDMA3 make a 3-dimension transfer?

Other Parts Discussed in Thread: TMS320C6455, SPRC234

Hello friends!

I am tring 3-dimension transfer with EDMA3 with aCnt = 8, bCnt = 2, cCnt = 4 and SourceBIndex, DestBIndex, SourceCIndex, DestCIndex = 16. However, it seems that the EDMA3 makes an 8 * 2 transfer as if cCnt = 1. What's the problem?

CCS 3.3.82.13, BIOS 5.31.02, Code Generation Tools 6.0.8, TMS320C6455 through XDS560PCI

Thanks!

  •  

    Are you sure that 3d transfers are supported by your EDMA peripheral? Do the next thing: Look what channel are you using (I guess you can find it in the hParam) and go to view->registers and copy and paste an image of this channel registers (paramsets) here. It should be filled by your paramset configuration. copy two images, before and after and you probably could obtain more help.

  • Yes, it supports 3D transfers because it succeeded once when I changed CSL_EDMA3_ITCCH_DIS into CSL_EDMA3_ITCCH_EN. But after that, the EDMA stopped working, even 1D transfer, until reset the power supply (not only reset the board).

    So, I think I must make some mistake with the EDMA3_OPT. I guess CSL_EDMA3_ITCCH_EN must be set to support 3D and CSL_EDMA3_TCCH_EN makes the EDMA trigger itself until the power supply is cut. Maybe CSL_EDMA3_ITCCH_EN, CSL_EDMA3_TCCH_DIS, CSL_EDMA3_ITCINT_DIS, CSL_EDMA3_TCINT_EN is correct. I'll have a try when I go to office and show the registers.

    Thanks!

  •  

    Well, I thing that we are missing a point... you want to perform a 3d transfer, uh? In my EDMA3 (dm6437) this is done chaining channels, but then you will need to program more than just one channel (two I guess). I have worked only with 1d transfers, but take in account this, so plus set ITTCH_EN and TCCH_EN (I think you do not need to enable any interrupt) you will need to program a TCC code to trigger a second channel in order to do a 3d dimension transfer...

  • It looks like this is merely a misunderstanding of how 'chaining' works with the EDMA3 module. I suggest making sure you understand what the TCCH and ITCCH are used for (sections 2.8 and 3.4.5 of the EDMA3 User's Guide). If you do not have intermediate chaining enabled and only send one event to the EDMA for that channel, then only one A*B transfer will occur.

  • Let's put 3D aside and try AB transfer with cCNT = 1 first. I called CSL_edma3HwChannelControl in two ways, but got different results, which may be "EDMA stopped working" as I said before.

     

  • It is very confused that it works after deleting two UNUSED params. The stack is 0x6000 bytes and does not overflow.

  • I do not see any explicit reason this would fail with the added arguments (although from what I can see of the code there's no real reason to pass any of these arguments yet). Have you tried stepping through the CSL call to see why it's failing? The source is all available in the CSL download from the web. You could potentially add the source file to your project to allow for source-level debugging of why this call is failing. I do not see where the EDMA registers are filled in so I presume these to be correct already (and the placement of the function shouldn't have any impact anyway).

  • Yes. When the EDMA stopped working, I run edma_sub_frame_xfer of sprc234 Chip Support Library for 6455, but it continued. I found the bit of ESR is always 1 that caused the EDMA stop working.

    Now, I abandon CSL and read/write EDMA3 registers directly, and it works well.

    Thank you very much!

  • Odd that the ESR bit gets stuck high. As soon as a '1' is written to that register the event should be submitted to the transfer controller at which point the ESR.n bit gets cleared. I see no reason why calls into the CSL would cause this bit to get 'stuck' (or for that matter why the event would not get transferred to the TC). In any case I am glad to hear you found a workaround for the time being.

  • Even though this thread is a few months old, it shows up in the Popular list. So it would be good to address the title of the thread, "How does EDMA3 make a 3-dimension transfer?"

    The PaRAM Sets contain all the information needed to perform a 3D transfer, A/B/C counts and B/C indexes.

    The intention of this structure is to provide a means to transfer an Array (ACNT bytes) or a Frame (ACNT*BCNT bytes) in response to a single event trigger from a peripheral, and then to be ready to transfer another Array or Frame in response to the next single event trigger. This can then continue until a Block (ACNT*BCNT*CCNT bytes) has been transferred.

    Multiple sequential events are required to get the complete Block transferred. In fact, either BCNT*CCNT or CCNT events will be required to complete the transfer of the full Block.

    For the case of a memory-to-memory copy, you would like to supply only one trigger event and then have the entire Block be transferred. This can be done using self-chaining.

    Chaining is the process where the end of a transfer or an intermediate transfer can trigger a DMA channel to run. The DMA channel is selected by setting OPT.TCC to the channel number to which you want to chain. Then the OPT.TCCHEN and OPT.ITCCHEN bits can be set to enable chaining at the end of the full transfer or at the end of each intermediate transfer.

    Self-chaining is implemented by setting OPT.TCC to the channel number of the channel that is programmed for the memory-to-memory transfer. If you program the PaRAM set for channel 5, for example, to do a 3D memory-to-memory transfer, you would set OPT.TCC=5 and OPT.ITCCHEN=1 and OPT.TCCHEN=0 and OPT.SYNCDIM=ABSYNC. When you manually trigger DMA channel 5, the first ACNT*BCNT Frame will be transferred (decrementing CCNT) and a chain event will be sent back around to DMA channel 5 again. This then triggers the 2nd Frame, decrements CCNT, and sends another chain event back around.

    This continues until CCNT decrements to 0. This would trigger another chain event if OPT.TCCHEN=1, but since you set OPT.TCCHEN=0, there will not be another chain event and the sequence will finally come to a halt. If you want to get an interrupt or at least set an IPR bit to indicate when the transfer is complete, you can set OPT.TCINTEN before starting the transfer sequence.

    The EDMA3 components, and linking, and chaining, are explained in a training video for the C6474. The general information on transfers will apply to all EDMA3 implementations, but some devices will have different event sources, different number of PaRAM sets and channels, and so on. In the Training section of TI.com, is the training video set for the C6474. The EDMA3/QDMA/IDMA Module may have some useful examples. You can find the complete video set at http://focus.ti.com/docs/training/catalog/events/event.jhtml?sku=OLT110002