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OMAP5 pinctrl settings for GPMC multiplexed address and data pins

Nick Thompson
Intellectual 330 points

The pins for GPMC multiplexed address and data, for example 'gpmc_ad0', are of course inputs and outputs during a read cycle. That's out for the address and in for the data during the same access cycle.

What pinmux setting should I have in the CONTROL_CORE_PAD0_C2C_DATAIN0_PAD1_C2C_DATAIN1 register at address 0x4A00285C for example? Currently I have 0x010c010c set in there. I seem to be able to write to devices, but can't read the data back - this might be more to do with the GPMC timings, rather than the pinmux settings, but the access cycle seems okay on the bus.

Thanks,

Nick.

  • 0
    TI__Guru**** 161600 points

    Hi Nick,

    Pinmux settings are correct. The value you read 0x010C010C corresponds to:

    bit field [4:0] C2C_DATAIN0_MUXMODE = 0x4 => gpmc_ad0 selected on device pad

    bit [8] C2C_DATAIN0_INPUTENABLE = 0x1 => input buffer cell enabled

    bit field [18:16] C2C_DATAIN1_MUXMODE = 0x4 => select gpmc_ad1

    bit [24] C2C_DATAIN1_INPUTENABLE = 0x1 => input buffer cell enabled

    Best Regards,

    Yordan