Couldn't detect SATA hard disk

bob lee

Other Parts Discussed in Thread: PMP, DM385

Hi ,

Based on dm8148 evm board, our custom board have one sata port an one msata port.But the board couldn't detect the sata hard disk in linux.

Need your help and thank you for advance.

Bob

over 11 years ago

0 Pavel Botev over 11 years ago

TI__Guru**** 170625 points

Bob,

bob lee said:
our custom board have one sata port an one msata port

So, you have two ports: 1 SATA port and 1 mSATA port. And HDD can not be detected on both ports or you can detect HDD on SATA port and can not detect HDD on mSATA port? Could you please provide console log output?

Reading the DM814x datasheet, it seems to me that you can have only one port:

Serial ATA (SATA) 3.0 Gbps Controller With Integrated PHY
– Direct Interface to One Hard Disk Drive
– Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
– Supports Port Multiplier and Command-Based Switching

8.18 Serial ATA Controller (SATA)

The Serial ATA (SATA) peripheral provides a direct interface to one hard disk drive (SATA 300) or up to
15 hard disk drives using a Port Multiplier

Please go through the below wiki pages and see if you will find something there:

http://processors.wiki.ti.com/index.php/DM814x_AM387x_PSP_User_Guide#SATA_Driver

The SATA subsystem supports one 3Gbps SATA host port capable of supporting Port Multiplier and direct connect SATA devices.

http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.02_Release_Notes#SATA

http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.02_Release_Notes#SATA_2

http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.02_Feature_Performance_Guide#SATA_Driver

http://processors.wiki.ti.com/index.php/TI_SATA_FAQ

http://processors.wiki.ti.com/index.php/EZSDK_Using_SATA_drive_for_Data

http://processors.wiki.ti.com/index.php/Linux_Core_SATA_User%27s_Guide

http://processors.wiki.ti.com/index.php/Sitara_PSP_Test_Setup#SATA

We have also two silicon errata for SATA:

Advisory 2.1.27 SATA: Unable to Operate Both SATA and VOUT0 Without SATA Locking Up.
Advisory 2.1.28 SATA: Link Establishment Fails With SATA GEN3 Capable Targets

Regards,
Pavel

0 bob lee over 11 years ago in reply to Pavel Botev

Genius 3210 points

Hi Pavel,

Our custom have two sata ports.One is for sata disk,and another is for msata disk.

Both ports couldn't detect HDD.

Here is the log below.

omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
omap_uart.3: ttyO3 at MMIO 0x481a6000 (irq = 44) is a OMAP UART3
omap_uart.4: ttyO4 at MMIO 0x481a8000 (irq = 45) is a OMAP UART4
omap_uart.5: ttyO5 at MMIO 0x481aa000 (irq = 46) is a OMAP UART5
brd: module loaded
loop: module loaded
ahci ahci.0: forcing PORTS_IMPL to 0x1
ahci ahci.0: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
ahci ahci.0: flags: ncq sntf pm led clo only pmp pio slum part ccc apst
scsi0 : ahci_platform
ata1: SATA max UDMA/133 irq_stat 0x00400040, connection status changed irq 16
omap2-nand driver initializing
NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung )
Creating 6 MTD partitions on "omap2-nand.0":
0x000000000000-0x000000020000 : "U-Boot-min"
0x000000020000-0x000000260000 : "U-Boot"
0x000000260000-0x000000280000 : "U-Boot Env"
0x000000280000-0x0000006c0000 : "Kernel"
0x0000006c0000-0x00000cee0000 : "File System"
0x00000cee0000-0x000010000000 : "Reserved"
davinci_mdio davinci_mdio.0: davinci mdio revision 1.6
davinci_mdio davinci_mdio.0: detected phy mask fffffff9
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[1]: device 0:01, driver RTL821x Gigabit Ethernet
davinci_mdio davinci_mdio.0: phy[2]: device 0:02, driver RTL821x Gigabit Ethernet
CAN device driver interface
CAN bus driver for Bosch D_CAN controller 1.0
d_can d_can: d_can device registered (irq=52, irq_obj=53)
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver dm9601
usbcore: registered new interface driver cdc_acm
cdc_acm: v0.26:USB Abstract Control Model driver for USB modems and ISDN adapters
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
mice: PS/2 mouse device common for all mice
qt602240_ts 1-004a: __qt602240_read_reg: i2c transfer failed
qt602240_ts: probe of 1-004a failed with error -5
omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0
i2c /dev entries driver
Linux video capture interface: v2.00
usbcore: registered new interface driver uvcvideo
USB Video Class driver (v1.0.0)
OMAP Watchdog Timer Rev 0x00: initial timeout 60 sec
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
usbcore: registered new interface driver snd-usb-audio
asoc: tlv320aic3x-hifi <-> davinci-mcasp.2 mapping ok
ALSA device list:
#0: TI81XX EVM
IPVS: Registered protocols ()
IPVS: Connection hash table configured (size=4096, memory=32Kbytes)
IPVS: ipvs loaded.
TCP cubic registered
NET: Registered protocol family 17
can: controller area network core (rev 20090105 abi 8)
NET: Registered protocol family 29
can: raw protocol (rev 20090105)
can: broadcast manager protocol (rev 20090105 t)
Registering the dns_resolver key type
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
omap_voltage_late_init: Voltage driver support not added
Power Management for TI81XX.
Detected MACID=84:7e:40:ea:5f:6c
omap_rtc omap_rtc: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
ata1.15: Port Multiplier 1.2, 0x197b:0x3202 r0, 2 ports, feat 0x5/0xf
ata1.00: hard resetting link
ata1.00: SATA link down (SStatus 0 SControl 320)
ata1.01: hard resetting link
ata1.01: SATA link down (SStatus 0 SControl 320)
ata1: EH complete
RAMDISK: gzip image found at block 0
VFS: Mounted root (ext2 filesystem) on device 1:0.
devtmpfs: mounted
Freeing init memory: 204K
INIT: version 2.86 booting
Please wait: booting...
Error opening /dev/fb0: No such file or directory
Starting udev
WARNING: -e needs -E or -F
udevd (80): /proc/80/oom_adj is deprecated, please use /proc/80/oom_score_adj instead.
Remounting root file system...
Caching udev devnodes
ALSA: Restoring mixer settings...
No state is present for card EVM
Found hardware: "" "" "" "" ""
Hardware is initialized using a generic method
No state is present for card EVM
Configuring e2fsprogs.
update-alternatives: Error: cannot register alternative chattr to /usr/bin/chattr since it is already registered to /bin/chattr
update-alternatives: Linking //sbin/uuidd to uuidd.util-linux-ng
Configuring update-modules.
Configuring dbus.
Adding system startup for /etc/init.d/dbus-1.
Configuring network interfaces...
CPSW phy found : id is : 0x1cc912

Bob

0 bob lee over 11 years ago in reply to bob lee

Genius 3210 points

Hi Pavel,

Our HW engineer tell me that I should set the clock for sata to 20MHz.

I don't find the configuration now.

Is it in the function "static int ti81xx_ahci_plat_init(struct device *dev, void __iomem *base)"?

} else {
   /* Configuring for 100Mhz clock source on TI814x */
   writel(TI814X_SATA_PHY_CFGRX0_VAL,
    base + TI814X_SATA_PHY_CFGRX0_OFFSET);
   writel(TI814X_SATA_PHY_CFGRX1_VAL,
    base + TI814X_SATA_PHY_CFGRX1_OFFSET);
   writel(TI814X_SATA_PHY_CFGRX2_VAL,
    base + TI814X_SATA_PHY_CFGRX2_OFFSET);
   writel(TI814X_SATA_PHY_CFGRX3_VAL,
    base + TI814X_SATA_PHY_CFGRX3_OFFSET);
   writel(TI814X_SATA_PHY_CFGTX0_VAL,
    base + TI814X_SATA_PHY_CFGTX0_OFFSET);
   writel(TI814X_SATA_PHY_CFGTX1_VAL,
    base + TI814X_SATA_PHY_CFGTX1_OFFSET);
   writel(TI814X_SATA_PHY_CFGTX2_VAL,
    base + TI814X_SATA_PHY_CFGTX2_OFFSET);
   writel(TI814X_SATA_PHY_CFGTX3_VAL,
    base + TI814X_SATA_PHY_CFGTX3_OFFSET);
  }

Bob

0 Pavel Botev over 11 years ago in reply to bob lee

TI__Guru**** 170625 points

Bob,

This is what we have in DM814x SATA TRM:

21.2.1 Clock Control

The selection for the input clock source for the SERDES, i.e., the 20 MHz reference cock or the 100 MHz differential clock, is configured via one of the SATA PLL Configuration register fields (CFGPLL0. SEL_IN_FREQ bit field located @ 0x4814_0720) where 0/1 implies external SERDES differential input/ reference 20 MHz clock input source. Note that the SATA PLL configuration registers are accessed from the device configuration register space and these registers lie within the control module space which is found in a different location from where the the SATA peripheral and PHY registers reside.

The register/bit that controls which clock (100M or 20M) to supply the SATA is:

SATA_PLLCFG0[31] SEL_IN_FREQ - select input frequency, 0x0: 100M, 0x1: 20M, at address 0x48140720.

In u-boot, the SW configures the SATA PLL for 20MHz:

u-boot-2010.06-psp04.04.00.01/board/ti/ti8148/evm.c

static void sata_pll_config()
{
   __raw_writel(0xC12C003C, SATA_PLLCFG1);
   __raw_writel(0x004008E0, SATA_PLLCFG3);
   delay(0xFFFF);

   __raw_writel(0x80000004, SATA_PLLCFG0);
   delay(0xFFFF);

   /* Enable PLL LDO */
   __raw_writel(0x80000014, SATA_PLLCFG0);
   delay(0xFFFF);

   /* Enable DIG LDO, ENBGSC_REF, PLL LDO */
   __raw_writel(0x80000016, SATA_PLLCFG0);
   delay(0xFFFF);

   __raw_writel(0xC0000017, SATA_PLLCFG0);
   delay(0xFFFF);

   /* wait for ADPLL lock */
   while(((__raw_readl(SATA_PLLSTATUS) & 0x01) == 0x0));

}

Thus we have SATA_PLLCFG0[31] SEL_IN_FREQ = 1 (20MHz)

But in the linux kernel, the SW configures the SATA PLL for 100MHz:

linux-2.6.37-psp04.04.00.01/arch/arm/mach-omap2/devices.c

static inline void ti814x_sata_pllcfg(void)
{
   if (!cpu_is_ti814x())
       return;

   if ((cpu_is_ti814x()) && (!cpu_is_dm385())) {
       /* Configure 100Mhz clock source on DM814x */

       /* Configure SATA0 PLL -applies for TI814x*/
       omap_ctrl_writel(0x00000004, TI814X_CONTROL_SATA_PLLCFG0);
       udelay(100);
       /* cfgpll1 (for 100 MHz Operation) */
       omap_ctrl_writel(0x812C003C, TI814X_CONTROL_SATA_PLLCFG1);
       udelay(2000);
       omap_ctrl_writel(0x004008E0, TI814X_CONTROL_SATA_PLLCFG3);
       udelay(2000);
       /* wait for bias to be stable */
       omap_ctrl_writel(0x00000014, TI814X_CONTROL_SATA_PLLCFG0);
       udelay(850);
       omap_ctrl_writel(0x00000016, TI814X_CONTROL_SATA_PLLCFG0);
       udelay(60);
       /* cfgpll0 Replaced 0xC00000016 to 0x40000016 for 100MHz
       * Usage instead of 20MHz
       */
       omap_ctrl_writel(0x40000016, TI814X_CONTROL_SATA_PLLCFG0);
       udelay(2000);

       /* cfgpll0 Replaced 0xC0007077 with 0x40007077 for
       * 100MHz Usage instead of 20MHz
       */
       omap_ctrl_writel(0x40007077, TI814X_CONTROL_SATA_PLLCFG0);

       while (!(omap_ctrl_readl(TI814X_CONTROL_SATA_PLLSTATUS) & 0x1))
           cpu_relax();
   } else {
       /* Configure 20Mhz clock source on ti813x */
   }

}

Thus we end up with SATA_PLLCFG0[31] SEL_IN_FREQ = 0 (100MHz)

As the comment state, you should replace 0x40007077 with 0xC0007077 in the last write:

/* cfgpll0 Replaced 0xC0007077 with 0x40007077 for
       * 100MHz Usage instead of 20MHz
       */
        - omap_ctrl_writel(0x40007077, TI814X_CONTROL_SATA_PLLCFG0);

       + omap_ctrl_writel(0xC0007077, TI814X_CONTROL_SATA_PLLCFG0);

       while (!(omap_ctrl_readl(TI814X_CONTROL_SATA_PLLSTATUS) & 0x1))
           cpu_relax();
   } else {
       /* Configure 20Mhz clock source on ti813x */
   }

}

Regards,
Pavel

0 bob lee over 11 years ago in reply to Pavel Botev

Genius 3210 points

Hi Pavel,

The configuration in my kernel is the same as yours.But the sata hdd still don't work.

Is there any other configuration related to the sata driver?

Bob

0 bob lee over 11 years ago in reply to bob lee

Genius 3210 points

Hi Pavel,

It's ok now.

Thank you very much.

Bob

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Couldn't detect SATA hard disk