EVM6748 and DMA from the A-to-D converter

Hi Walter,

Walter Snafu said:

I am using the LogicPD EVM board(s) with the TMS320C6748 SOM.  I understand that there is a 10-bit, 20 M sample/Second A-to-D converter on-board somewhere.  I presume it is connected to the SMA connector labeled "connector H" on their Quick Start Guide.  ???  Am I right? 

For the latest version of the quick start guide please see":

http://support.logicpd.com/downloads/1213/

Walter Snafu said:

I need to DMA data from the A-to-D converter into memory at a high rate of speed.  So I am looking for info on how to do that.  I suspect there is already a test program available (in the bundle that came from LogicPD). Such as their program test_cvideo or test_svideo.  ??? I dunno. 

Can you steer me toward the information I need?

Also, you can get the board's schematic, documentations and examples at (click at Kit contents):

http://www.logicpd.com/products/development-kits/zoom-omap-l138-experimenter-kit

You need to have an account in Logic's website to get some of the documents. You can also register your board there. 

 Also, please check the: http://tiexpressdsp.com/index.php/Getting_Started_Guide_for_C6748 for more software.

Walter Snafu said:

[Note: By the way, my board differs from the photo given on page 8 of their Quick Start Guide 1014618rev4_OMAP-L138_EVM_QSG.pdf.  That is, on my board the connectors G & H are swapped -- And on my board the connectors C & D are swapped -- compared to their diagram.  I presume this is no big deal, as I am able to identify the connectors by eye.]

 If you can, please send that to Logic PD directly:

http://www.logicpd.com/products/development-kits/zoom-omap-l138-experimenter-kit   -> click on the Support tab.

I've been studying the schematics for the LogicPD EVM board.  The A/D converter chip is 10-bits, and can inherently run at 20 Mega Samples per Second.  However, it appears to go through a parallel to serial data bus "extender" that slows down the effective sampling rate. So what is the effective max sampling rate.  I can't find that info.

Also, the board comes with test programs, for testing various on-board functions.  The test for that A/D converter runs at a rate of ~4.672 Mega Samples per second (= 73000x64).  Is that the fastest it can go?  I can't find that info.

For my project, the sampling rate clock needs to come from off-board.  Is there a way to do that with this EVM board? I'm hoping to get somewhere near 15 Mega Samples per Second?  Can that be achieved with this board?

If not, then does the board have the 'hooks' for me to add-on a daughter-board (with an A/D converter, etc.) that would achieve my goal?  (Even if I have to build the daughter card?)  I would like to DMA the samples into memory, using a sampling-clock that comes from off-board. Hopefully near 15 Mega Samples per Second.  Hopefully with 10-bit accuracy or better.

Thanks for your help.

[Note:  These are questions about the LogicPD EVM board and its capabilities, not about DSP or the TMS320C6748 per se. That is why I originally posted this thread elsewhere.]

Gus,

Thank you, Thank you!  That is exactly the info I needed.

To review, I am to remove the User Interface board to free-up connector J29 for my daughter card.  Then the sampling clock can come from off-board, directly into the daughter card, for controlling the sampling times.  That is exactly what I need. (I suspect many people have the same need, which is why I'm spelling out the details here, so as to make sure the details are right, and also to share those details with others.)

According to the LogicPD EVM baseboard schematic, the following 41 UPP signals are available on connector J29:

• UPP_XD[0 thru 15]
• UPP_CH1_D[0 thru 15]
• UPP_CH0_ENABLE
• UPP_CH1_ENABLE
• UPP_CH0_START
• UPP_CH1_START
• UPP_CH0_CLK
• UPP_CH1_CLK
• UPP_CH0_WAIT
• UPP_CH1_WAIT
• UPP_2xTXCLK

Most of those names are easily recognizable as corresponding to the names defined in the video and in the webpage (By the way, the link to the Universal Parallel Port User Guide given on that webpage is broken. And I can't locate that User Guide through searching.) However, two of the names are unmentioned elsewhere and need clarification here. What are these?

• UPP_2xTXCLK
• UPP_XD[0 thru 15] [I'm guessing that corresponds somehow to channel 2 of the UPP?]

 *************************************

 Also, perhaps an alternative solution is available (and easier than building a daughter card?). That is, is there a way to replace the system clock (crystal?) with a clock that comes from off-board?  Then, with proper software settings (of the on-board phase-locked-loop multipliers and dividers, and timers for the UPP), the system can run at approximately its usual speed, while still locking the sampling rate to an off-board clock.  This approach has the benefit of not requiring a daughter card, but has the added requirement for carefully setting the phase-locked-loop and other parameters to make all the clocks work properly.  Is this approach workable?  Would it require potentially 'dangerous' de-soldering of parts from the EVM board, potentially mangling the board?  Could an apt technician accomplish it? (As I said, this might well be easier than building a daughter card.)

Thanks for your help.

Walter Snafu said:

By the way, the link to the Universal Parallel Port User Guide given on that webpage is broken

We'll need to have that corrected.  It appears that document links change when new revisions of the document are released.  Thanks for pointing it out.  You can find the new user guide at this link:

http://www.ti.com/litv/pdf/sprugj5b

In the future, it is best to go to the product folder for your device.  There you will find all user guides and app notes for your device.

http://focus.ti.com/docs/prod/folders/print/tms320c6748.html

Walter Snafu said:

Also, perhaps an alternative solution is available (and easier than building a daughter card?). That is, is there a way to replace the system clock (crystal?) with a clock that comes from off-board?

See the "Device Clocking" and "UPP Clocking" section in your device system reference guide (look in the product folder for your device).  You can generate the UPP clock from the DSP clock.  You can use this spreadsheet to figure out if you can get the right frequencies:

http://tiexpressdsp.com/index.php/Programming_PLL_Controllers_on_OMAP-L1x8/C674x/AM18xx

Walter Snafu said:

Would it require potentially 'dangerous' de-soldering of parts from the EVM board, potentially mangling the board?  Could an apt technician accomplish it?

I'll say that it is not impossible to do this.  You would have to de-pop the 24 MHz crystal and two caps and somehow add wires through which you can feed your external clock.  There is a risk of damaging the board as you say though given the small form factor of the C6748 SOM.  I would see if I could generate the required frequency from the existing 24MHz clock and device PLL and dividers first though.

I found yet another alternative way to accomplish this. 

The A/D converter is on the UI board, and it gets its sampling-clock from a programmable phase-locked loop (designated U43) also on the UI board.  This phase-locked-loop has an external crystal (designated Y3). The spec sheet for the phase-locked-loop (and its application report) indicates it can by "synchronized" to an external clock (though at the moment, it is not clear how to do that...  Perhaps that is yet another avenue for solution???). 

From the spec sheet, it does seem possible to disconnect the crystal, and run an external clock through this chip (bypassing the phase locked loop) and simply use the dividers on this chip to obtain a desired integer sub-frequency locked to the external clock.  This seems like another plausible way to accomplish my goal. 

These parts (Y3 and U43) are visible on the underside of the UI board, and seem a more likely candidate for de-soldering (Y3) and attaching wires for an external clock. Reprogramming this chip would also be required, under control of the SOM.  (A useful example of this programming is given in the LogicPD project file "test_upp".) 

This is still risky, but more do-able than re-soldering the SOM.

Also, it does look like the A/D converter has a full parallel bus all the way to the processor (contrary to my earlier impression), and therefore the sampling rate may well approach the limit of the A/D converter part (which is 20 Mega Samples per Second, with 10-bit resolution).

Thanks again for your help.  I hope I am passing on useful information to others.