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OMAP-L138 clock freq

Stephen Lin40335
Intellectual 275 points
Other Parts Discussed in Thread: OMAP-L138

What's the lowest core frequency that OMAP-L138 can run at without disrupting the basic functionality of the chip (such as its DSP algorithm function)The spec is listing it at 300Mhz, but we might just need to run it at 100Mhz or lower. Is it a problem?

  • 0
    TI__Mastermind 28991 points

    See your the Device Clocking section of your reference guide for some basic info on how the CPU and the peripherals on the device are clocked.  You can run the CPU as low as you want, but due to the way the device is clocked, changing the CPU clock may affect some peripherals.  May want to look into ASYNC3_CLKSRC which basically makes some peripherals immune to changes in CPU frequency.

    Note that you can reduce the core voltage at lower CPU frequencies to save power.  The frequency/voltage combination is referred to as an operating point.  Regardless of whether you scale the voltage, you can scale down the frequency to any level you want as long as you stay below the maximum support frequency at a particular operating point.

  • 0 in reply to Gus Martinez
    TI__Mastermind 28991 points

    Correcting typo...

    See the Device Clocking section of your system reference guide for some basic info on how the CPU and the peripherals on the device are clocked.

  • 0 in reply to Gus Martinez
    Intellectual 275 points

    I am not understanding that table very well. Can you give me a example on how should I interpret table 6-2 under device clocking section if I am running say like 100Mhz CPU clock (main purpose is to reduce power)?  Which peripheral would not work?

    Are those peripherals listed under PLL0_SYSCLK1, PLL0_SYSCLK2, PLL0_SYSCLK4, PLL0_SYSCLK6 won't work since it's required to have fixed ratio to DSP clock? Please confirm. thanks.

    On the other note, how low can I lower my voltage down to if my frequency is reduced from 300Mhz to 100Mhz (assuming I/O core voltage is running @ 1.8v)?

  • 0 in reply to Stephen Lin40335
    TI__Mastermind 28991 points

    See figure 7-1 (PLLC structure) in the L138 system reference guide.  The clock right at the output of the PLLEN mux is fed to all the SYSCLK dividers. You can change the DSP/ARM clock simply by changing the SYSCLK1/SYSCLK6 dividers.  However, as you point out, there is a ratio requirement for some dividers so you would to change those too. 

    For example, you could go to a DSP frequency of 100MHz by changing PLLDIV1 from /1 to /3 (assuming clock at output of PLLEN mux was 300MHz), but you would also have to increment the divider on SYSCLK2, SYSCLK4, and SYSCLK6 to meet the ratio requirement.  If you were using a peripheral like UART0 (SYSCLK2), which derives its baud rate from SYSCLK2, its operating baud rate would be changed.  On the other hand, notice that UART1/2 would not be affected since they are on a different clocking domain.

    The only voltage you can scale "on the fly" is the core voltage (CVDD).  For that you need a programmable power supply.  If you see the L138 EVM, it has a programmable supply which is controlled via I2C.  There is power management software (supported on both Linux and BIOS) which include libraries that help you do frequency and voltage scaling btw.

    You might find this wiki site useful:

    http://tiexpressdsp.com/index.php/Programming_PLL_Controllers_on_OMAP-L1x8/C674x/AM18xx

  • 0 in reply to Gus Martinez
    Intellectual 275 points

    Thanks for the answer, I am getting better in understanding this issue.

    Few more questions to clear my mind along with the explanation you had previously:

    1. Using the example we had before, if PLLEN mux is 300Mhz, then PLLDIV1 = /3, PLLDIV2 = /6, PLLDIV3 = N/A, PLLDIV4 = /12, PLLDIV6 = /3, PLLDIV7 = N/A. In this case, does it mean PLL0_SYSCLK2 = 50Mhz (b/c of 300Mhz / 6 from PLLDIV2) can be used to run all peripherals under PLL0_SYSCLK2 domain and still meet its design spec. In another word, can USB2.0 perform like USB2.0 HS (480Mb) Host/Client when its clock running at 50Mhz?  According to the xls sheet, this clocking frequency didn't produce any timing violations....
    2. How do we take all those frequency reduction in different domain and convert them into power saving for the core? Or we are still waiting for OMAP-L138 team to publish the final power-consumption table for this?
    3. For the "on the fly" core voltage CVDD that canbe used to perform power management feature for OMAP-L138, can you point me to more information on this? Are there documents that I can read about how exact to reduce power using this feature? Or how much power would be saved if this feature is turned on?

    Thanks! Stephen

  • 0 in reply to Stephen Lin40335
    TI__Mastermind 28991 points

    Stephen Lin said:
    Using the example we had before, if PLLEN mux is 300Mhz, then PLLDIV1 = /3, PLLDIV2 = /6, PLLDIV3 = N/A, PLLDIV4 = /12, PLLDIV6 = /3, PLLDIV7 = N/A. In this case, does it mean PLL0_SYSCLK2 = 50Mhz (b/c of 300Mhz / 6 from PLLDIV2) can be used to run all peripherals under PLL0_SYSCLK2 domain and still meet its design spec. In another word, can USB2.0 perform like USB2.0 HS (480Mb) Host/Client when its clock running at 50Mhz?  According to the xls sheet, this clocking frequency didn't produce any timing violations....

    Take a look at the USB Clocking section in the system reference guide.  The USB 2.0 subsystem does require a reference clock for its internal PLL.  This clock can be from either USB_REFCLKIN or from PLL0.AUXCLK (which is basically CLKIN/OSCIN).  The specific frequencies required are given in the table titled USB Clock Multiplexing Options.

    One thing to note is that the SYSCLK2 in your example is the "module" clock which, in the case of USB, is used to access registers and other operations not related to the actual I/O clock.  The I/O clock is derived from the USB_REFCLKIN or AUXCLK is previously described. 

    Stephen Lin said:
    How do we take all those frequency reduction in different domain and convert them into power saving for the core? Or we are still waiting for OMAP-L138 team to publish the final power-consumption table for this?

    Yes, the power spreadsheet is still under development.  Once ready it will allow you quickly estimate the power consumption of the device under different voltage & frequency operating points and peripheral use case scenarios.

    Stephen Lin said:
    For the "on the fly" core voltage CVDD that canbe used to perform power management feature for OMAP-L138, can you point me to more information on this? Are there documents that I can read about how exact to reduce power using this feature? Or how much power would be saved if this feature is turned on?

    See this post:

    http://e2e.ti.com/support/arm174_microprocessors/omap_applications_processors/f/42/p/30972/118515.aspx#118515