MCASP does not startup

Hi Dimitry,

Are you using McASP starterware code in SYSBIOS ?

Could you please elaborate a bit on your requirement and problem.

 Thanks for the answer, Titus!

yes, I use StarterWare routine in my SYS/BIOS application for MCASP initialize. I need just generate external clock of MCASP for my external ADC.

I use my own board on the OMAP'L138 based. All examples of bios_psp and StarterWare works well on my board.

Before my code also works well.

You can see my MCASP initialization function bellow:

void McASPI2SConfigure(void)
{
	// power on the GPIO device in the Power sleep controller
		    Psc_ModuleClkCtrl((Psc_DevId)CSL_LPSC_INST_GPIO_0, CSL_PSC_GPIO, TRUE);
	unsigned int savePinMux = 0;

	    /*
	    ** Clearing the bits in context and retaining the other bit values
	    ** of PINMUX0 register.
	    */
	    savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
	                       ~(SYSCFG_PINMUX0_PINMUX0_23_20);

	    /*
	    ** Performing the actual Pin Multiplexing to select mandatory pins in
	    ** PINMUX0  register.
	    */
	    HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
	         ( PINMUX0_MCASP0_AHCLKX_ENABLE | savePinMux);



	    McASPRxReset(SOC_MCASP_0_CTRL_REGS);
	        McASPTxReset(SOC_MCASP_0_CTRL_REGS);


	        /* configure the clock for transmitter */
	        McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 0, 1874);
	        McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
	        McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
	                             0x00, 0xFF);

	        /* Enable synchronization of RX and TX sections  */
	            McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

	        /*
	        ** Configure the McASP pins
	        ** Input - Frame Sync, Clock and Serializer Rx
	        ** Output - Serializer Tx is connected to the input of the codec
	        */
	        McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AHCLKX);
	        McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AHCLKX);
	        McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);


}

But now I can uderstand why my code stay in infinite cycle in this function:

void McASPTxClkStart(unsigned int baseAddr, unsigned int clkSrc)
{
    /* Release the high frequency clock from reset*/
    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XHCLKRST; 
    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XHCLKRST)   // from here can not move forward. Why?
          != MCASP_GBLCTL_XHCLKRST) ;
     
    if(clkSrc != MCASP_TX_CLK_EXTERNAL)
    {
       /* Release the clock from reset*/
        HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XCLKRST; 
        while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XCLKRST) 
              != MCASP_GBLCTL_XCLKRST) ;
    }
}

Any idea?

Hi,

Thanks for your update.

If you see section 25.2.4.1.2 in the omapl138 TRM, it is mentioned clearly in step 4 that, in order to take the high-frequency serial clock dividers out of reset and to start the respective high frequency Tx. & Rx. serial clocks AHCLKX & AHCLKR, it needs to set the XHCLKRST bit for the transmitter in GBLCTL McASP register. So, in your case, i guess it is not happening and you need to ensure in the code that, before you proceed, you have to read back from GBLCTL register whether the XHCLKRST bit for the transmitter you wrote is successfully latched in GBLCTL or not.

From the above point, it is obvious that, in your case, it is not setting the XHCLKRST bit for the transmitter and it is not latched properly in GBLCTL McASP register. Kindly confirm this behaviour happens in your code while debugging it step by step and keep watching the GBLCTL McASP register. This is the reason, your program stops in the below routine and it stays there in infinite cycle since it keeps waiting for the while condition to satisfy in order to release the high frequency clock from reset, but the program is not able to exit from the infinite cycle function routine below:

HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XHCLKRST;

while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XHCLKRST)   

To get more info. on the above, please check section 25.2.4.1.2 in the OMAPl138 TRM as below:

http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

Thanks & regards,

Sivaraj K

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