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VC5509A EMIF Timing

Herb
Prodigy 675 points

I have a question about the EMIF timing on this DSP. The datasheet is showing a timing diagram referencing to CLKOUT but also says the CLKOUT is the same as internal clock. I know the cycle times are calculated based on the internal clock but not sure about the delay numbers of the generated signals, say the delay of CE0 after which clock edge? Is there a timing diagram kind of showing an example where CLKOUT is different from internal clock?

  • 0
    TI__Prodigy 120 points

    Herb,

    The EMIF module clock is always the CPU clock as you stated. Asynchronous memory does not use a clock so there should not be a clkout waveform in the diagram. The waveform labeled as CLKOUT in Figure 5-6 and 5-7 should have been labeled CPU clock. Thus, the timing diagrams are always valid.

    -Christy