Hi,
I'm using a SSD1963 LCD controller to interface a 320x240 pixel LCD with AM437x using 16-bit parallel in RFBI mode.
I would like to keep the pixel format to 24bpp and I see I can transfer 2 pixel data in 3 clocks with the right register configurations. The SSD1963 specifies the 16-bit packed interface as shown in below.
Will the AM437x DSS adhere to this kind pixel data packing when I program 24bpp pixel over 16-bit and 3 clock parallel interface?
